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AD883B Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD883B Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 11 page AD538 –7– REV. C STABILITY PRECAUTIONS At higher frequencies, the multistaged signal path of the AD538, as illustrated in Figure 10, can result in large phase shifts. If a condition of high incremental gain exists along that path (e.g., VO = VY × V Z /VX = 10 V × 10 mV/10 mV = 10 V so that ∆V O / ∆V X = 1000), then small amounts of capacitive feedback from VO to the current inputs IZ or IX can result in instability. Appropriate care should be exercised in board layout to pre- vent capacitive feedback mechanisms under these conditions. LOGe IY VY Ln Y LOGe IZ VZ Ln Z LOGe IX VX Ln X 0.2 M 5 BUFFER + ++ – Ln Z – Ln X M(Ln Z – Ln X) M(Ln Z – Ln X) +Ln Y VO = VY VZ VX M ANTILOGe Figure 10. Model Circuit USING THE VOLTAGE REFERENCES A stable bandgap voltage reference for scaling is included in the AD538. It is laser-trimmed to provide a selectable voltage out- put of +10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any voltages between +2 V and +10.2 V buffered as shown in Figure 11. The output impedance at Pin 5 is approximately 5 k Ω. Note that any loading of this pin will produce an error in the +10 V reference voltage. External loads on the +2 V output should be greater than 500 k Ω to maintain errors less than 1%. 25k 25k LOG RATIO 100 25k 25k ANTILOG LOG OUTPUT 100 AD538 INTERNAL VOLTAGE REFERENCE I VO IZ VZ B REF OUT –VS +VS +2V IY A D IX VX C PWR GND SIGNAL GND VY 118 17 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 50k 11.5k +2V TO +10.2V BUFFERED Figure 11. +2 V to +10.2 V Adjustable Reference In situations not requiring both reference levels, the +2 V output can be converted to a buffered output by tying Pins 4 and 5 together. If both references are required simultaneously, the +10 V output should be used directly and the +2 V output should be externally buffered. ONE-QUADRANT MULTIPLICATION/DIVISION Figure 12 shows how the AD538 may be easily configured as a precision one-quadrant multiplier/divider. The transfer function VOUT = VY (VZ /VX) allows “three” independent input variables, a calculation not available with a conventional multiplier. In addition, the 1000:1 (i.e., 10 mV to 10 V) input dynamic range of the AD538 greatly exceeds that of analog multipliers comput- ing one-quadrant multiplication and division. 25k 25k LOG RATIO 100 25k 25k ANTILOG LOG OUTPUT 100 AD538 INTERNAL VOLTAGE REFERENCE I VO IZ VZ B +10V +2V IY A D IX VX C PWR GND SIGNAL GND VY 1 18 17 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 VZ INPUT +15V –15V OUTPUT VX INPUT VY INPUT IN4148 VOUT = VY ( ) VZ VX Figure 12. One-Quadrant Combination Multiplier/Divider By simply connecting the input VX (Pin 15) to the +10 V refer- ence (Pin 4), and tying the log-ratio output at B to the antilog input at C, the AD538 can be configured as a one-quadrant analog multiplier with 10-volt scaling. If 2-volt scaling is desired, VX can be tied to the +2 V reference. When the input VX is tied to the +10 V reference terminal, the multiplier transfer function becomes: V O = VY V Z 10 V As a multiplier, this circuit provides a typical bandwidth of 400 kHz with values of VX, VY or VZ varying over a 100:1 range (i.e., 100 mV to 10 V). The maximum error with a 100 mV to 10 V range for the two input variables will typically be +0.5% of reading. Using the optional Z offset trim scheme, as shown in Figure 13, this error can be reduced to +0.25% of reading. By using the +10 V reference as the VY input, the circuit of Figure 12 is configured as a one-quadrant divider with a fixed scale factor. As with the one-quadrant multiplier, the inputs accept only single (positive) polarity signals. The output of the one-quadrant divider with a +10 V scale factor is: V O = 10V V Z V X The typical bandwidth of this circuit is 370 kHz with 1 V to 10 V denominator input levels. At lower amplitudes, the band- width gradually decreases to approximately 200 kHz at the 2 mV input level. |
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Descrizione simile - AD883B |
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