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AD5310BRM Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD5310BRM Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 12 page AD5310 –4– REV. A PIN CONFIGURATIONS TOP VIEW (Not to Scale) 6 5 4 1 2 3 VOUT GND VDD SYNC SCLK DIN AD5310 SOT-23 TOP VIEW (Not to Scale) 8 7 6 5 1 2 3 4 NC AD5310 SYNC VOUT GND VDD SCLK DIN NC SOIC NC = NO CONNECT PIN FUNCTION DESCRIPTIONS SOT-23 Pin Numbers Pin No. Mnemonic Function 1VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation. 2 GND Ground reference point for all circuitry on the part. 3VDD Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and VDD should be de- coupled to GND. 4 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 5 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 6 SYNC Level triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. |
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