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AD1833 Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD1833 Scheda tecnica(HTML) 8 Page - Analog Devices |
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8 / 20 page  REV. 0 AD1833 –8– FUNCTIONAL DESCRIPTION Device Architecture The AD1833 is a 6-channel audio DAC featuring multibit Sigma-Delta ( Σ-∆) technology. The AD1833 features three stereo converters (giving six channels) where each stereo channel is controlled by a common bit-clock (BCLK) and synchroniza- tion signal (L/ RCLK). Interpolator The interpolator consists of up to three stages of sample rate doubling and half-band filtering followed by a 16 sample zero order hold. The sample rate doubling is achieved by zero stuff- ing the input samples, and a digital half band filter is then used to remove any images above the band of interest and to bring the zero samples to their correct values. By selecting different input sample rates, one, two, or all three stages of doubling may be switched in. This allows for three different sample rate inputs. All three doubling stages are used with the 48 kHz input sample rate, with the 96 kHz input sample rate only two doubling stages are used, and with the 192 kHz input sample rate only one doubling stage is used. In each case the input sample frequency is increased to 384 kHz. The Zero- Order Hold (ZOH) holds the interpolator samples for upsampling by the modulator. This is done at a rate 16 times the interpola- tor output sample rate. Modulator The modulator is a 6-bit, second-order implementation and uses data scrambling techniques to achieve perfect linearity. The modulator samples the output of the interpolator stage(s) at a rate of 6.144 MHz. OPERATING FEATURES SPI Register Definitions The SPI port allows flexible control of the devices’ program- mable functions. It is organized around nine registers; six individual channel VOLUME registers and three CONTROL registers. Each WRITE operation to the AD1833 SPI control port requires 16 bits of serial data in MSB-first format. The four most significant bits are used to select one of nine registers (seven register addresses are reserved), and the bottom 10 bits are then written to that register. This allows a write to one of the nine registers in a single 16-bit transaction. The SPI CCLK signal is used to clock in the data. The incoming data should change on the falling edge of this signal and remain valid during the rising edge. At the end of the 16 CCLK periods, the CLATCH signal should rise to latch the data internally into the AD1833. See Figure 2. The serial interface format used on the Control Port utilizes a 16-bit serial word as shown in Table I. The 16-bit word is divided into several fields: Bits 15–12 define the register address, Bits 11 and 10 are reserved and must be programmed to 0, and Bits 9–0 are the data field (which has specific definitions, depending on the register selected). Table I. Control Port Map Register Address Reserved 1 Data Field 15 2 14 13 12 11 10 9876543210 NOTES 1Must be programmed to zero. 2Bit 15 = MSB Bit 15 Bit 14 Bit 13 Bit 12 Register Function 0 0 0 0 DAC Control I 0 0 0 1 DAC Control II 0 0 1 0 DAC Volume 1 0 0 1 1 DAC Volume 2 0 1 0 0 DAC Volume 3 0 1 0 1 DAC Volume 4 0 1 1 0 DAC Volume 5 0 1 1 1 DAC Volume 6 1 0 0 0 DAC Control III 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved |
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