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CXA3026AQ Scheda tecnica(PDF) 11 Page - Sony Corporation |
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CXA3026AQ Scheda tecnica(HTML) 11 Page - Sony Corporation |
11 / 29 page —11— CXA3026AQ 8bit CLKOUT DATA 8bit CLKOUT DATA CLK CLK CXA3026AQ CXA3026AQ CLK RESETN CLK RESETN A B 2. Straight mode (See Application Circuits1- (4), (5) and (6).) Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. The A/D converter can operate at Fc (min.) = 100MSPS in this mode. Digital input level and supply voltage settings The logic input level for the CXA3026AQ supports ECL, PECL and TTL levels. The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. Digital input level ECL PECL TTL –5 V 0 V 0 V 0 V +5 V +5 V ±5 V +5 V +5 V (1) (4) (2) (5) (3) (6) DVEE3 DGND3 Supply voltage Application circuits Table 3. Logic Input Level and Power Supply Settings 8bit CLKOUT DATA 8bit CLKOUT DATA CLK CXA3026AQ CXA3026AQ A B CLK RESETN CLK RESETN CLK RESET signal RESET signal (Reset period) (Reset period) When the RESET signal is used. When the RESET signal is not used. |
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