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CXA3026AQ Scheda tecnica(PDF) 4 Page - Sony Corporation |
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CXA3026AQ Scheda tecnica(HTML) 4 Page - Sony Corporation |
4 / 29 page —4— CXA3026AQ Pin Description and I/O Pin Equivalent Circuit Analog ground. Separated from the digital ground. Analog power supply. Separated from the digital power supply. Digital ground. Digital power supply. Digital power supply. Ground for ECL input. +5 V for PECL and TTL input. Digital power supply. –5 V for ECL input. Ground for PECL and TTL input. No connected pin. Not connected with the internal circuits. Clock input. CLK/E complementary input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. Reset input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. RESETN/E complementary input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. 3, 10 5, 8 20, 29 32, 41 19, 30 31, 42 12 1 16, 17 18 13 14 48 47 AGND AVCC DGND1 DGND2 DVCC1 DVCC2 DGND3 DVEE3 N.C. CLK/E CLKN/E RESETN/E RESET/E GND +5 V (typ.) GND +5 V (typ.) +5 V (Typ.) (With a single power supply) GND (With dual power supplies) GND (With a single power supply) –5 V (Typ.) (With dual power supplies) ECL/ PECL Pin No. Symbol I I I I I/O Standard voltage level Equivalent circuit Description DGND3 DVEE3 r r r r 13 14 48 47 |
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