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SN74ACT72241L50RJ Scheda tecnica(PDF) 7 Page - Texas Instruments |
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SN74ACT72241L50RJ Scheda tecnica(HTML) 7 Page - Texas Instruments |
7 / 21 page SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L 512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9 SYNCHRONOUS FIRST IN, FIRST OUT MEMORIES SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 RS tw(RS) tsu(RS) th(RS) REN1, REN2 tsu(RS) th(RS) WEN1 tsu(RS) th(RS) WEN2/LD (see Note A) EF, PAE tpd(RS-O) FF, PAF tpd(RS-O) Q0 − Q8 tpd(RS-O) See Note B NOTES: A. Holding WEN2/LD high during reset makes it act as a second write enable. Holding WEN2/LD low during reset makes it act as a load enable for the programmable flag offset registers. B. After reset, the outputs are low if OE is low and at the high-impedance level if OE is high. C. The clocks (RCLK, WCLK) can be free running during reset. Figure 2. Reset Timing |
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