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SN74ACT2236-40FN Scheda tecnica(PDF) 4 Page - Texas Instruments

Il numero della parte SN74ACT2236-40FN
Spiegazioni elettronici  1024x9x2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SN74ACT2236-40FN Scheda tecnica(HTML) 4 Page - Texas Instruments

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SN74ACT2236
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST IN, FIRST OUT MEMORY
SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AF/AEA,
AF/AEB
15, 30
O
Almost full/almost empty flags. The almost-full/almost-empty A flag (AF/AEA) is defined by the
almost-full/almost-empty offset value for FIFO A (X). AF/AEA is high when FIFO A contains X or less
words or 1024 − X words. AF/AEA is low when FIFO A contains between X + 1 or 1023 − X words.
The operation of the almost-full/almost-empty B flag (AF/AEB) is the same as AF/AEA for FIFO B.
A0 − A8
4 − 8, 10 − 13
I/O
A data inputs and outputs
B0 − B8
32 − 35,
37 − 41
I/O
B data inputs and outputs
DAF, DBF
21, 24
I
Define-flag inputs. The high-to-low transition of DAF stores the binary value on A0 − A8 as the
almost-full/almost-empty offset value for FIFO A (X). The high-to-low transition of DBF stores the
binary value of B0−B8 as the almost-full/almost-empty offset value for FIFO B (Y).
EMPTYA,
EMPTYB
20, 25
O
Empty flags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high
when they are not empty.
FULLA,
FULLB
18, 27
O
Full flags. FULLA and FULLB are low when their corresponding memories are full and high when they
are not full.
HFA, HFB
16, 29
O
Half-full flags. HFA and HFB are high when their corresponding memories contain 512 or more
words, and low when they contain 511 or less words.
LDCKA,
LDCKB
17, 28
I
Load clocks. Data on A0−A8 is written into FIFO A on a low-to-high transition of LDCKA. Data on
B0 − B8 is written into FIFO B on a low-to-high transition of LDCKB. When the FIFOs are full, LDCKA
and LDCKB have no effect on the data residing in memory.
DIR, OE
2, 43
I
Enable inputs. DIR and OE control the transceiver functions. When OE is high, both A0 − A8 and
B0 − B8 are in the high-impedance state and can be used as inputs. With OE low and DIR high, the
A bus is in the high-impedance state and B bus is active. When both OE and DIR are low, the A bus
is active and the B bus is in the high-impedance state.
RSTA, RSTB
22, 23
I
Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA,
EMPTYB, FULLA, FULLB, and AF/AEB high. Both FIFOs must be reset upon power up.
SAB, SBA
1, 44
I
Select-control inputs. SAB and SBA select whether real-time or stored data is transferred. A low level
selects real-time data, and a high level selects stored data. Eight fundamental bus-management
functions can be performed as shown in Figure 1.
UNCKA,
UNCKB
19, 26
I
Unload clocks. Data in FIFO A is read to B0 − B8 on a low-to-high transition of UNCKB. Data in FIFO
B is read to A0 − A8 on a low-to-high transition of UNCKB. When the FIFOs are empty, UNCKA and
UNCKB have no effect on data residing in memory.
programming procedure for AF/AEA
The almost-full/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The
almost-full/almost-empty offset value FIFO A (X) and for FIFO B (Y) are either a user-defined value or the default
values of X = 256 and Y = 256. Below are instructions to program AF/AEA using both methods. AF/AEB is
programmed in the same manner for FIFO B.
user-defined X
Take DAF from high to low. This stores A0 thru A8 as X.
If RSTA is not already low, take RSTA high.
With DAF held low, take RSTA high. This defines the AF/AEA flag using X.
To retain the current offset for the next reset, keep DAF low.
default X
To redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset cycle.


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