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74HCT573BQ-Q100 Scheda tecnica(PDF) 4 Page - NXP Semiconductors |
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74HCT573BQ-Q100 Scheda tecnica(HTML) 4 Page - NXP Semiconductors |
4 / 19 page 74HC_HCT573_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 16 August 2012 4 of 19 NXP Semiconductors 74HC573-Q100; 74HCT573-Q100 Octal D-type transparent latch; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as supply pin or input Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 aaa-003603 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 OE VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 74HC573-Q100 74HCT573-Q100 aaa-003604 Transparent top view Q7 D6 D7 Q6 D5 Q5 D4 Q4 D3 Q3 D2 Q2 D1 Q1 D0 GND(1) Q0 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area 74HC573-Q100 74HCT573-Q100 Table 2. Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) LE 11 latch enable input (active HIGH) Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state latch output VCC 20 supply voltage |
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