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UC1525B-SP Scheda tecnica(PDF) 1 Page - Texas Instruments |
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UC1525B-SP Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 13 page 1 FEATURES DESCRIPTION UC1525B-SP www.ti.com............................................................................................................................................................................................... SLUS874 – JANUARY 2009 RAD-TOLERANT CLASS-V REGULATING PULSE WIDTH MODULATOR • QML-V Qualified, SMD 5962-89511 • Rad-Tolerant: 30 kRad (Si) TID (1) The UC1525B pulse width modulator integrated circuit is designed to offer improved performance and • 8-V to 35-V Operation lowered external parts count when used in designing • 5.1-V Buried Zener Reference Trimmed to all types of switching power supplies. The on-chip ±0.75% 5.1-V buried zener reference is trimmed to ±0.75%, • 100-Hz to 400-kHz Oscillator Range and the input common-mode range of the error amplifier includes the reference voltage, eliminating • Separate Oscillator Sync Terminal external resistors. A sync input to the oscillator allows • Adjustable Deadtime Control multiple units to be slaved or a single unit to be • Internal Soft Start synchronized to an external system clock. A single resistor between the CT and the discharge terminals • Pulse-by-Pulse Shutdown provide a wide range of dead-time adjustment. These • Input Undervoltage Lockout With Hysteresis devices also feature built-in soft-start circuitry with • Latching PWM to Prevent Multiple Pulses only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry • Dual Source/Sink Output Drivers and the output stages, providing instantaneous turn • Low Cross Conduction Output Stage off through the PWM latch with pulsed shutdown, as • Tighter Reference Specifications well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The UC1525B output stage (1) Radiation tolerance is a typical value based upon initial device features NOR logic, giving a LOW output for an OFF qualification with dose rate = 10 mrad/sec. Radiation Lot Acceptance Testing is available - contact factory for details. state. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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