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ISLA224P25 Scheda tecnica(PDF) 11 Page - Intersil Corporation |
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ISLA224P25 Scheda tecnica(HTML) 11 Page - Intersil Corporation |
11 / 32 page ISLA224P12 11 FN7983.3 August 17, 2012 FIGURE 4. CMOS Timing Diagrams (Continued) CLKN CLKP INP INN tA CLKOUT tCPD D[13:0] LATENCY = L CYCLES tDC tPD A DATA N-L B DATA N-L A DATA N-L+1 B DATA N-L+1 B DATA N-1 A DATA N B DATA N Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL CONDITION MIN (Note 5) TYP MAX (Note 5) UNITS ADC OUTPUT Aperture Delay tA 114 ps RMS Aperture Jitter jA 75 fs Input Clock to Output Clock Propagation Delay tCPD AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C 1.65 2.4 3 ns tCPD AVDD, OVDD = 1.8V, TA = +25°C 1.9 2.3 2.75 ns Relative Input Clock to Output Clock Propagation Delay (Note 13) dtCPD AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C -450 450 ps Input Clock to Data Propagation Delay tPD 1.65 2.4 3.5 ns Output Clock to Data Propagation Delay, LVDS Mode tDC Rising/Falling Edge -0.1 0.16 0.5 ns Output Clock to Data Propagation Delay, CMOS Mode tDC Rising/Falling Edge -0.1 0.2 0.65 ns Synchronous Clock Divider Reset Setup Time (with Respect to the Positive Edge of CLKP) tRSTS 0.4 0.06 ns Synchronous Clock Divider Reset Hold Time (with Respect to the Positive Edge of CLKP) tRSTH 0.02 0.35 ns Synchronous Clock Divider Reset Recovery Time tRSTRT DLL recovery time after Synchronous Reset 52 µs Latency (Pipeline Delay) L 10 cycles |
Codice articolo simile - ISLA224P25 |
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Descrizione simile - ISLA224P25 |
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