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TPA2080D1YZGR Scheda tecnica(PDF) 2 Page - Texas Instruments |
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TPA2080D1YZGR Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 20 page D1 D2 C1 C2 B1 B2 OUT– PGND AGND N/C OUT+ BGND EN A1 A2 SW D3 C3 B3 VBAT A3 PVDD IN– IN+ YZG Package (Top View) TPA2080D1 SLOS733 – JANUARY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM DEVICE PINOUT 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA2080D1 |
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