SMJ320C26

DIGITAL SIGNAL PROCESSOR

SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001

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POST OFFICE BOX 1443

architecture

The SMJ320C26 architecture is based on the SMJ320C25 with a different internal RAM and ROM configuration.

The SMJ320C26 integrates 256 words of on-chip ROM and 1568 words of on-chip RAM compared to 4K words

of on-chip ROM and 544 words of on-chip RAM for the SMJ320C25. The SMJ320C26 is pin for pin compatible

with the SMJ320C25.

Increased throughput on the SMJ320C26 for many DSP applications is accomplished by means of single cycle

multiply/accumulate instructions with a data move option, eight auxiliary registers with a dedicated arithmetic

unit, and faster I/O necessary for data intensive signal processing.

The architectural design of the SMJ320C26 emphasizes overall speed, communication, and flexibility in the

processor configuration. Control signals and instructions provide floating point support, block memory transfers,

communication to slower off-chip devices, and multiprocessing implementations.

Three large on-chip RAM blocks, configurable either as separate program and data spaces or as three

contiguous data blocks, provide increased flexibility in system design. Programs of up to 256 words can be

masked into the internal program ROM. The remainder of the 64K-word program memory space is located

externally. Large programs can execute at full speed from this memory space. Programs can also be

downloaded from slow external memory to high speed on-chip RAM. A data memory address space of 64K

words is included to facilitate implementation of DSP algorithms. The VLSI implementation of the SMJ320C26

incorporates all of these features as well as many others, including a hardware timer, serial port, and block data

transfer capabilities.

32-bit ALU accumulator

The SMJ320C26 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic and

logic instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch

instructions dependent on the status of the ALU or a single bit in a word. These instructions provide the following

capabilities:

One input to the ALU is always provided from the accumulator, and the other input may be provided from the

Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the RAM on the

data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the

accumulator.

The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the

output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The

contents of the accumulator remain unchanged.

scaling shifter

The SMJ320C26 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to

the ALU. The scaling shifter produces a left shift of 0 to 16-bits on the input data, as specified in the instruction

word. The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign

extended, depending upon the value of the SXM (sign extension mode) bit of status register STO.

16

× 16 bit parallel multiplier

The SMJ320C26 has a 16

× 16 bit-hardware multiplier, which is capable of computing a signed or unsigned

32-bit product in a single machine cycle. The multiplier has the following two associated registers: