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SM320C32PCMM50EP Scheda tecnica(PDF) 6 Page - Texas Instruments |
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SM320C32PCMM50EP Scheda tecnica(HTML) 6 Page - Texas Instruments |
6 / 44 page SM320C32EP DIGITAL SIGNAL PROCESSOR SGUS038 − AUGUST 2002 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Functions (Continued) PIN CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ DESCRIPTION TYPE† NAME CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ DESCRIPTION TYPE† NO. CONTROL SIGNALS (9 PINS) RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. INT3 − INT0 4 I External interrupts CONTROL SIGNALS (9 PINS) (CONTINUED) IACK 1 O/Z Interrupt acknowledge. IACK is set to a logic high by the IACK instruction. This signal can be used to indicate the beginning or end of an interrupt-service routine. S MCBL / MP 1 I Microcomputer bootloader / microprocessor mode XF1 − XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I / Os or used to support interlocked-processor instructions. S R SERIAL PORT SIGNALS (6 PINS) CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter. S R DX0 1 I/O/Z Data transmit output. Serial port 0 transmits serial data on DX0. S R FSX0 1 I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data process over DX0. S R CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S R DR0 1 I/O/Z Data receive. Serial port 0 receives serial data on DR0. S R FSR0 1 I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the receive-data process over DR0. S R TIMER SIGNALS (2 PINS) TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. S R TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. S R CLOCK SIGNALS (3 PINS) CLKIN 1 I Input to the internal oscillator from an external clock source H1 1 O/Z External H1 clock. H1 has a period equal to twice CLKIN. S H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. S RESERVED (5 PINS) EMU0 − EMU2 3 I Reserved for emulation. Use 18 k Ω−22 kΩ pullup resistors to 5 V. EMU3 1 O/Z Reserved for emulation S SHZ 1 I Shutdown high impedance. When active, SHZ shuts down the C32 and places all 3-state I/O pins in the high-impedance state. SHZ is used for board-level testing to ensure that no dual drive conditions occur. CAUTION: A low on SHZ corrupts C32 memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor is 0.1 µF. |
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