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SN74SSTUB32864ZKER Scheda tecnica(PDF) 11 Page - Texas Instruments |
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SN74SSTUB32864ZKER Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 18 page www.ti.com ELECTRICAL CHARACTERISTICS SN74SSTUB32864 SCAS791A – OCTOBER 2006 – REVISED SEPTEMBER 2007 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT IOH = –100 μA 1.7V to 1.9V VCC–0.2 VOH Q outputs V IOH = –6 mA 1.7V 1.3 IOL = 100 μA 1.7V to 1.9V 0.2 VOL Q outputs V IOL = 6 mA 1.7V 0.4 II All inputs(2) VI = VCC or GND 1.9V ±5 μA Static standby RESET = GND 200 μA ICC IO = 0 1.9V RESET = VCC, VI = VIH(AC) or Static operating 40 mA VIL(AC) RESET = VCC, VI = VIH(AC) or Dynamic operating – clock VIL(AC), CLK and CLK switching 45 μA/MHz only 50% duty cycle Dynamic operating – per RESET = VCC, VI = VIH(AC) or ICCD each data input, 1:1 IO = 0 1.8V 43 VIL(AC), CLK and CLK switching μA clock configuration 50% duty cycle, one data input MHz/ Dynamic operating – per switching at one-half clock D input each data input, 1:2 60 frequency, 50% duty cycle configuration Chip-select-enabled RESET = VCC, VI = VIH(AC) or low-power active mode – VIL(AC), CLK and CLK switching 45 μA/MHz clock only 50% duty cycle Chip-select-enabled RESET = VCC, VI = VIH(AC) or ICCDLP low-power active mode - IO = 0 1.8V 2 VIL(AC), CLK and CLK switching μA clock 1:1 configuration 50% duty cycle, one data input MHz/ Chip-select-enabled switching at one-half clock D input low-power active mode – 3 frequency, 50% duty cycle 1:2 configuration Data inputs, CSR VI = VREF ± 250 mV 2.5 3 3.5 Ci CLK, CLK VICR = 0.9 V, VI(PP) = 600 mV 1.8V 2 3 pF RESET VI = VCC or GND 4 (1) All typical values are at VCC = 1.8 V, TA = 25°C. (2) Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open. Copyright © 2006–2007, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): SN74SSTUB32864 |
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