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TS3DS10224RUKR Scheda tecnica(PDF) 2 Page - Texas Instruments |
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TS3DS10224RUKR Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 17 page 0 1 1 0 0 1 0 1 SAO SBO SAI SBI INA INB OUTA1 OUTA0 OUTB1 OUTB0 + - + - + - + - ENA ENB + - + - TS3DS10224 SCDS318 – JUNE 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE(1)(2) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C QFN Tape and Reel TS3DS10224RUKR ZTB (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. PIN FUNCTIONS PIN NAME PIN TYPE DESCRIPTION SAI Input Control input SAO Input Control input SBI Input Control input SBO Input Control input ENA Input Enable INA+ I/O Input A INA – I/O Input A ENB Input Enable INB+ I/O Input B INB- I/O Input B OUTB0 – I/O Output B0 OUTB0+ I/O Output B0 OUTB1 – I/O Output B1 OUTB1+ I/O Output B1 GND Ground Ground VCC Power Power supply OUTA0 – I/O Output A0 OUTA0+ I/O Output A0 OUTA1 – I/O Output A1 OUTA1+ I/O Output A1 LOGIC DIAGRAM 2 Copyright © 2011, Texas Instruments Incorporated |
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