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74FCT807CTPYPBLANK Scheda tecnica(PDF) 4 Page - Integrated Device Technology |
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74FCT807CTPYPBLANK Scheda tecnica(HTML) 4 Page - Integrated Device Technology |
4 / 8 page 4 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT74FCT807BT/CT FAST CMOS 1-TO-10 CLOCK DRIVER NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. SWITCHING CHARACTERISTICS OVER OPERATING RANGE - COMMERCIAL(3,4) FCT807BT FCT807CT Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Unit tPLH PropagationDelay 1.3 2.7 1.3 2.5 ns tPHL tR OutputRiseTime — 1.5 — 1.5 ns tF OutputFallTime — 1.5 — 1.5 ns tSK(O) Output skew: skew between outputs of all banks of — 0.5 — 0.25 ns samepackage(inputstiedtogether) tSK(P) Pulseskew:skewbetweenoppositetransitions — 0.5 — 0.35 ns ofsameoutput(|tPHL-–tPLH|) tSK(T) Packageskew:skewbetweenoutputsofdifferent — 0.9 — 0.65 ns packages at same power supply voltage, temperature,packagetypeandspeedgrade 50 Ωto VCC/2, CL = 10pF (See figure 1) or 50 Ωac termination, CL = 10pF (See figure 2) f ≤100MHz Outputsconnectedin groups of two FCT807BT FCT807CT Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Unit tPLH PropagationDelay 1.5 3.8 1.5 3.5 ns tPHL tR OutputRiseTime — 1.5 — 1.5 ns tF OutputFallTime — 1.5 — 1.5 ns tSK(O) Output skew: skew between outputs of all banks of — 0.5 — 0.25 ns samepackage(inputstiedtogether) tSK(P) Pulseskew:skewbetweenoppositetransitions — 0.5 — 0.35 ns ofsameoutput(|tPHL-–tPLH|) tSK(T) Packageskew:skewbetweenoutputsofdifferent — 0.9 — 0.75 ns packages at same power supply voltage, temperature,packagetypeandspeedgrade CL = 30pF f ≤67MHz (See figure 3) FCT807BT FCT807CT Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Unit tPLH PropagationDelay 1.5 3.8 1.5 3.5 ns tPHL tR OutputRiseTime — 1.5 — 1.5 ns tF OutputFallTime — 1.5 — 1.5 ns tSK(O) Output skew: skew between outputs of all banks of — 0.5 — 0.35 ns samepackage(inputstiedtogether) tSK(P) Pulseskew:skewbetweenoppositetransitions — 0.6 — 0.45 ns ofsameoutput(|tPHL-–tPLH|) tSK(T) Packageskew:skewbetweenoutputsofdifferent — 1 — 0.75 ns packages at same power supply voltage, temperature,packagetypeandspeedgrade CL = 30pF f ≤40MHz (See figure 4) |
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