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DAC1008D750HN Scheda tecnica(PDF) 11 Page - NXP Semiconductors |
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DAC1008D750HN Scheda tecnica(HTML) 11 Page - NXP Semiconductors |
11 / 99 page DAC1008D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 5 January 2011 11 of 99 NXP Semiconductors DAC1008D750 2 ×, 4× or 8× interpolating DAC with JESD204A [1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. [2] Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It reflects the delay required by DAC1008D750 to lock to a JESD204A stream. It supposes that the TX is already transmitting K28.5 characters in error-free conditions. [3] CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80 Ω and 120 Ω (see Figure 15) should be connected across the pins. [4] |Vgpd| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance and the inductance between the receiver and the driver circuit ground voltage. [5] Vin_p and Vin_n inputs are differential CML inputs. They are terminated internally to Vtt via 50 Ω (see Figure 4). [6] SYNC_OUTP/SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80 Ω and 120 Ω. [7] Optimum performances at high sampling rate (> 650 Msps) will be achieved with VDDA(1V8) =1.8 V ± 2% [8] IMD3 rejection with −6 dBFS/tone. ACPR adjacent channel power ratio NCO on; 4× interpolation; fs = 737.28 Msps; fo = 96 MHz [7] 1 carrier; BW = 5 MHz C - 67 - dBc 2 carriers; BW = 10 MHz C - 64 - dBc 4 carriers; BW = 20 MHz C - 60 - dBc NCO on; 4 × interpolation; fs = 737.28 Msps; fo = 153.6 MHz [7] 1 carrier; BW = 5 MHz C - 67 - dBc 2 carriers; BW = 10 MHz C - 64 - dBc 4 carriers; BW = 20 MHz C - 59 - dBc NSD noise spectral density fs = 737.28 Msps; 4 × interpolation; fo = 153.6 MHz at 0 dBFS I [7] - −145 - dBm/Hz Table 5. Characteristics …continued VDDA(1V8) =VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.13 V to 3.47 V; AGND and GND are shorted together; Tamb = −40 °C to +85 °C; typical values measured at VDDA(1V8) =VDDD =1.8 V; VDDA(3V3) =3.3 V; Tamb =+25 °C; RL =50 Ω; IO(fs) =20mA; maximum sample rate; PLL off unless otherwise specified. Symbol Parameter Conditions Test[1] Min Typ Max Unit |
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