NBXDPA018

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2

FSEL

OE

GND

CLK

CLK

1

2

3

6

5

4

Table 1. PIN DESCRIPTION

Pin No.

Symbol

I/O

Description

1

OE

LVTTL/LVCMOS

Control Input

Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.

See OE pin description Table 2.

2

FSEL

LVTTL/LVCMOS

Control Input

Output Frequency Select Pin. Pin will default to logic HIGH when left open. See Output

Frequency Select pin description Table 3.

3

GND

Power Supply

Ground 0 V

4

CLK

LVDS Output

Non−Inverted Clock Output. Typically loaded with 100 W receiver termination resistor

across differential pair.

5

CLK

LVDS Output

Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across

differential pair.

6

Power Supply

Positive power supply voltage. Voltage should not exceed 2.5 V ±5% or 3.3 V ±10%.

Table 2. OUTPUT ENABLE TRI−STATE FUNCTION

OE Pin

Output Pins

Open

Active

HIGH Level

Active

LOW Level

High Z

Table 3. OUTPUT FREQUENCY SELECT

FSEL Pin

Output Frequency (MHz)

Open

(pin will float high)

155.52

HIGH Level

155.52

LOW Level

311.04

Table 4. ATTRIBUTES

Characteristic

Value

Input Default State Resistor

170 kW

ESD Protection

Human Body Model

Machine Model

2 kV

200 V

Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test

1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.

Table 5. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Units

Positive Power Supply

GND = 0 V

4.6

V

LVDS Output Current

Continuous

Surge

25

50

mA

Operating Temperature Range

−40 to +85

°C

Storage Temperature Range

−55 to +120

°C

Wave Solder

See Figure 6

260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.