18.0-21.0/36.0-42.0 GHz GaAs MMIC

Doubler and Power Amplifier

Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099

Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com

Characteristic Data and Specifications are subject to change without notice.

©2008 Mimix Broadband, Inc.

Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept

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App Note [1] Biasing

Id1<1mA, Id2=20mA, Id3=40mA, Id4=70mA, Id5=150mA, Id6=270mA. Separate biasing is recommended if the amplifier is to be used at high levels

of saturation, where gate rectification will alter the effective gate control voltage. As shown in the bonding diagram, it is possible to parallel stages

Vd(3,4,5) with Id(3,4,5)=260mA while maintaining satisfactory performance. For non-critical applications it is possible to parallel stages Vd(3,4,5,6)

together and adjust the common gate voltage Vg(3,4,5,6) for total drain current Id(total)=530mA. It is also recommended to use active biasing to

keep the currents constant as the RF power and temperature vary; this gives the most reproducible results. Depending on the supply voltage

available and the power dissipation constraints, the bias circuit may be a single transistor or a low power operational amplifier, with a low value

resistor in series with the drain supply used to sense the current. The gate of the pHEMT is controlled to maintain correct drain current and thus

drain voltage. The typical gate voltage needed to do this is -0.7V. Typically the gate is protected with Silicon diodes to limit the applied voltage. Also,

make sure to sequence the applied voltage to ensure negative gate bias is available before applying the positive drain supply.

App Note [2] Bias Arrangement -

For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain pad DC bypass capacitors

(~100-200 pF) can be combined. Additional DC bypass capacitance (~0.01 uF) is also recommended to all DC or combination (if gate or drains are

tied together) of DC bias pads. Vd(3,4,5,6) or Vg(3,4,5,6) have been tied together but can be left open.

For Individual Stage Bias (Recommended for saturated applications) -- Each DC pad (Vd1,2,3,4,5,6 and Vg1,2,3,4,5,6) needs to have DC bypass

capacitance (~100-200 pF) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended.

MTTF

MTTF is calculated from accelerated life-time data of single devices and assumes an isothermal back-plate.

X1001-BD

XX1001-BD, MTTF (yrs) vs. Backplate Temperature (°C)

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

55

65

75

85

95

Temperature (°C)

November 2008 - Rev 03-Nov-08