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FAN9612 Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor

Il numero della parte FAN9612
Spiegazioni elettronici  Design Consideration for Interleaved Boundary Conduction Mode PFC
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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AN-6086
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.4 • 4/22/10
4
4. Design Considerations
In this section, a design procedure is presented using the
schematic in Figure 7 as a reference. A 400W PFC
application with universal input range is selected as a
design example. The design specifications are as follows:
- Line voltage range: 85~265VAC (universal input),
50Hz
- Nominal output voltage and current: 400V/1A (400W)
- Holdup time requirement: Output voltage should not
drop below 330V during one line cycle
- Output voltage ripple: less than 8Vp-p
- Minimum switching frequency: higher than 50kHz
- Control Bandwidth: 5~10Hz
- Brownout protection line voltage: 70VAC
The design is for two identical converters, which deliver
half of the total output power (200W), respectively. VDD is
assumed to be supplied from auxiliary power supply.
Figure 7. Reference Circuit for Design Example of Interleaving BCM Boost PFC
[STEP-1] Boost Inductor Design
The boost inductor value is determined by the output
power and the minimum switching frequency. From
Equation 2, the minimum frequency with a given line
voltage and MOSFET on time is obtained as:
,
2
1
OUT
LINE
SW MIN
ON
OUT
VV
f
tV
=⋅
(3)
where:
VLINE is RMS line voltage;
tON is the MOSFET conduction time; and
VOUT is the output voltage.
The MOSFET conduction time with a given line voltage at
a nominal output power is given as:
,
2
2
OUT CH
ON
LINE
P
L
t
V
η
=
(4)
where:
η is the efficiency;
L is the boost inductance; and
POUT,CH is the nominal output power per channel
Using Equation 4, the minimum switching frequency of
Equation 3 can be expressed as:
2
LINE
LINE
,
,
2
2
OUT
SW MIN
OUT CH
OUT
VV
V
f
PL
V
η ⋅−
=⋅
⋅⋅
(5)


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