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SM320F28335-HT Scheda tecnica(PDF) 7 Page - Texas Instruments

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Il numero della parte SM320F28335-HT
Spiegazioni elettronici  Digital Signal Controller (DSC)
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Produttore elettronici  TI [Texas Instruments]
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SM320F28335-HT Scheda tecnica(HTML) 7 Page - Texas Instruments

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SM320F28335-HT
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SPRS682 – DECEMBER 2010
List of Tables
2-1
Hardware Features
.............................................................................................................. 12
2-2
Pin Out Information
.............................................................................................................. 13
2-3
Signal Descriptions
............................................................................................................... 18
3-1
Addresses of Flash Sectors
.................................................................................................... 29
3-2
Handling Security Code Locations
............................................................................................. 29
3-3
Wait-states
........................................................................................................................ 30
3-4
Boot Mode Selection
............................................................................................................. 33
3-5
Peripheral Frame 0 Registers
.................................................................................................. 38
3-6
Peripheral Frame 1 Registers
.................................................................................................. 38
3-7
Peripheral Frame 2 Registers
.................................................................................................. 39
3-8
Peripheral Frame 3 Registers
.................................................................................................. 39
3-9
Device Emulation Registers
..................................................................................................... 39
3-10
PIE Peripheral Interrupts
....................................................................................................... 42
3-11
PIE Configuration and Control Registers
...................................................................................... 43
3-12
External Interrupt Registers
..................................................................................................... 44
3-13
PLL, Clocking, Watchdog, and Low-Power Mode Registers
............................................................... 46
3-14
PLLCR Bit Descriptions
......................................................................................................... 48
3-15
CLKIN Divide Options
........................................................................................................... 48
3-16
Possible PLL Configuration Modes
............................................................................................ 48
3-17
Low-Power Modes
............................................................................................................... 50
4-1
CPU-Timers 0, 1, 2 Configuration and Control Registers
................................................................... 54
4-2
ePWM Control and Status Registers (default configuration in PF1)
....................................................... 56
4-3
ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible)
............................. 57
4-4
eCAP Control and Status Registers
........................................................................................... 61
4-5
eQEP Control and Status Registers
........................................................................................... 63
4-6
ADC Registers
................................................................................................................... 67
4-7
McBSP Register Summary
...................................................................................................... 71
4-8
3.3-V eCAN Transceivers
...................................................................................................... 73
4-9
CAN Register Map
.............................................................................................................. 76
4-10
SCI-A Registers
.................................................................................................................. 78
4-11
SCI-B Registers
.................................................................................................................. 78
4-12
SCI-C Registers
................................................................................................................. 78
4-13
SPI-A Registers
................................................................................................................... 81
4-14
I2C-A Registers
................................................................................................................... 84
4-15
GPIO Registers
.................................................................................................................. 86
4-16
GPIO-A Mux Peripheral Selection Matrix
.................................................................................... 87
4-17
GPIO-B Mux Peripheral Selection Matrix
.................................................................................... 88
4-18
GPIO-C Mux Peripheral Selection Matrix
.................................................................................... 89
4-19
XINTF Configuration and Control Register Mapping
........................................................................ 92
6-1
Current Consumption by Power Supply Pins
................................................................................. 96
6-2
Typical Current Consumption by Various Peripherals (at 150 MHz)
..................................................... 98
6-3
Clocking Nomenclature for TC = -55°C to 125°C (150-MHz Devices) ................................................... 103
6-4
Clocking Nomenclature for TC = 210°C (100-MHz Devices) .............................................................. 103
6-5
Input Clock Frequency
......................................................................................................... 104
6-6
XCLKIN Timing Requirements - PLL Enabled
............................................................................. 104
6-7
XCLKIN Timing Requirements - PLL Disabled
............................................................................. 104
6-8
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
...................................................... 104
Copyright © 2010, Texas Instruments Incorporated
List of Tables
7


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