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LC75366M Scheda tecnica(PDF) 6 Page - Sanyo Semicon Device |
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LC75366M Scheda tecnica(HTML) 6 Page - Sanyo Semicon Device |
6 / 11 page Pin Functions No. 4929-6/11 LC75366, 75366M Pin No. Symbol Function Note 1 20 2 3 19 18 4 17 5 16 6 15 7 14 12 9 10 11 8 13 L10dBIN R10dBIN LCT1 LCT2 RCT1 RCT2 L10dBOUT R10dBOUT L2dBIN R2dBIN L2dBOUT R2dBOUT LVref RVref S CL DI CE VDD VSS Input pins for the 10 dB step attenuator. Must be driven from a low impedance. Loudness connections. Connect a high band compensation capacitor between CT1 and 10dBIN and connect a low band compensation capacitor between CT2 and Vref. Output pins for the 10 dB step attenuator. These outputs must be received by a load of about 1 M Ω. Input pins for the 2 dB step attenuator. Must be driven from a low impedance. Output pins for the 2 dB step attenuator. These outputs must be received by a load of about 1 M Ω. Volume circuit common pins. The impedance of the pattern connected to these pins should be kept as low as possible. Since the capacitors between Vref and VSS form the residual resistance components when the volume is cut, adequate care must be taken in determining the value of these capacitors. Pin that selects the address code in the data format. Data will be accepted for an address code of 88 when this pin is tied to VDD, and for an address code of 89 when tied to VSS. Serial data and clock inputs for control Chip enable. The internally latched data is written and the analog switches operate when this pin goes from high to low. Data transfer is enabled when this pin is at the high level. These pins must be connected to the power supply. |
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