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ISL25700 Scheda tecnica(PDF) 7 Page - Intersil Corporation

Il numero della parte ISL25700
Spiegazioni elettronici  Programmable Temperature Controlled MOSFET Driver
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Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL25700
7
FN6885.0
September 3, 2010
tAA
(Note 11)
SCL Falling Edge to SDA
Output Data Valid
SCL falling edge crossing 30% of VI2C,
until SDA exits the 30% to 70% of
VI2C window
900
ns
tBUF
(Note 11)
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of VI2C during a
STOP condition, to SDA crossing 70%
of VI2C during the following START
condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VI2C crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VI2C crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VI2C.
600
ns
tHD:STA START Condition Hold Time
From SDA falling edge crossing 30%
of VI2C to SCL falling edge crossing
70% of VI2C
600
ns
tSU:DAT Input Data Setup Time
From SDA exiting the 30% to 70% of
VI2C window, to SCL rising edge
crossing 30% of VI2C
100
ns
tHD:DAT Input Data Hold Time
From SCL falling edge crossing 70% of
VI2C to SDA entering the 30% to 70%
of VI2C window
0
ns
tSU:STO STOP Condition Setup Time
From SCL rising edge crossing 70% of
VI2C, to SDA rising edge crossing 30%
of VI2C
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of
VI2C, until SDA enters the 30% to
70% of VI2C window
0
ns
tR
SDA and SCL Rise Time
From 30% to 70% of VI2C
20 +
0.1 * Cb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VI2C
20 +
0.1 * Cb
250
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Rpu
(Note 11)
SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
1
tWC
(Notes
11, 12)
Non-Volatile Write Cycle Time
15
20
ms
NOTES:
6. Typical values are for TA = +25°C and 12V supply voltage.
7. LSB: [VDAC255 – VDAC0]/255. VDAC255 and VDAC0 are the DAC output voltage when DAC register set to FF hex and 00 hex
respectively.
8. DNL = [VDACi – VDACi-1]/LSB-1, for i = 1 to 255. i is the DAC register setting.
9. INL = [VDACi – (i • LSB + VDAC0)]/LSB for i = 1 to 255.
10.
for i = 1 to 255 decimal, T = -40°C to +125°C, referenced to 40°C.
11. Limits established by characterization and are not production tested.
12. tWC is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the
end of the self-timed internal non-volatile write cycle. The Busy Polling method can be used to determine the end of the
non-volatile write cycle.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
14. B25/85 is a thermistor material specific constant; represents the slope of the Resistance vs. Temperature curve.
Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits
apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 6)
MAX
(Note 13) UNITS
TCV
VDACi T
() VDAC
i 40°C
()
VDACi 40°C
()
-------------------------------------------------------------------------
106
T40
()°C
----------------------------
×
=


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