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ISLA112P25MREP Scheda tecnica(PDF) 10 Page - Intersil Corporation |
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ISLA112P25MREP Scheda tecnica(HTML) 10 Page - Intersil Corporation |
10 / 29 page ISLA112P25MREP 10 FN7646.0 June 25, 2010 Latency (Pipeline Delay) L 7.5 cycles Over Voltage Recovery tOVR 1cycles SPI INTERFACE (Notes 12, 13) SCLK Period Write Operation t CLK Note 15 cycles (Note 12) Read Operation tCLK Note 15 cycles SCLK Duty Cycle (tHI/tCLK or tLO/tCLK) Read or Write Note 15 50 Note 15 % CSB↓ to SCLK↑ Setup Time Read or Write tS Note 15 cycles CSB↑ after SCLK↑ Hold Time Read or Write tH Note 15 cycles Data Valid to SCLK↑ Setup Time Write tDSW Note 15 cycles Data Valid after SCLK↑ Hold Time Write tDHW Note 15 cycles Data Valid after SCLK↓ Time Read tDVR Note 15 cycles Data Invalid after SCLK↑ Time Read tDHR Note 15 cycles Sleep Mode CSB↓ to SCLK↑ Setup Time (Note 14) Read or Write in Sleep Mode tS Note 15 µs NOTES: 10. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 11. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most applications. Contact factory for more info if needed.. 12. SPI Interface timing is directly proportional to the ADC sample period (4ns at 250MSPS). 13. The SPI may operate asynchronously with respect to the ADC sample clock. 14. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time (4ns min). 15. Refer to DSCC drawing number V62/10609 for min/max parameters. Switching Specifications (Continued) PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS |
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