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ADF7242 Scheda tecnica(PDF) 4 Page - Analog Devices |
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ADF7242 Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 108 page ADF7242 Rev. 0 | Page 4 of 108 GENERAL DESCRIPTION The ADF7242 is a highly integrated, low power, and high perfor- mance transceiver for operation in the global 2.4 GHz ISM band. It is designed with emphasis on flexibility, robustness, ease of use, and low current consumption. The IC supports the IEEE 802.15.4- 2006 2.4 GHz PHY requirements as well as proprietary GFSK/ FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. With a minimum number of external compo- nents, it achieves compliance with the FCC CFR47 Part 15, ETSI EN 300 440 (Equipment Class 2), ETSI EN 300 328 (FHSS, DR > 250 kbps), and ARIB STD T-66 standards. The ADF7242 complies with the IEEE 802.15.4-2006 2.4 GHz PHY requirements with a fixed data rate of 250 kbps and DSSS- OQPSK modulation. With its support of GFSK/FSK/GMSK/MSK modulation schemes, the IC can operate over a wide range of data rates from 50 kbps to 2 Mbps and is, therefore, equally suitable for proprietary applications in the areas of smart metering, industrial control, home and building automation, and consumer electronics. In addition, the agile frequency synthesizer of the ADF7242, together with short turnaround times, facilitates the implementation of FHSS systems. The transmitter path of the ADF7242 is based on a direct closed-loop VCO modulation scheme using a low noise fractional-N RF frequency synthesizer. The automatically calibrated VCO operates at twice the fundamental frequency to reduce spurious emissions and avoid PA pulling effects. The bandwidth of the RF frequency synthesizer is automatically optimized for transmit and receive operations to achieve optimum phase noise, modulation quality, and synthesizer settling time performance. The transmitter output power is programmable from −20 dBm to +4 dBm with automatic PA ramping to meet transient spurious specifications. An integrated biasing and control circuit is available in the IC to significantly simplify the interface to external PAs. The receive path is based on a zero-IF architecture enabling very high blocking resilience and selectivity performance, which are critical performance metrics in interference dominated environ- ments such as the 2.4 GHz band. In addition, the architecture does not suffer from any degradation of blocker rejection in the image channel, which is typically found in low IF receivers. In GFSK/FSK modes, the receiver features a high speed automatic frequency control (AFC) loop, which allows the frequency synthesizer to find and correct any frequency errors in the received packet. The IC can operate with a supply voltage between 1.8 V and 3.6 V with very low power consumption in receive and transmit modes while maintaining its excellent RF performance, making it espe- cially suitable for battery-powered systems. The ADF7242 features a flexible dual-port RF interface that can be used with an external LNA and/or PA in addition to support- ing switched antenna diversity. The ADF7242 incorporates a very low power custom 8-bit processor that supports a number of transceiver management functions. These functions are handled by the two main mod- ules of the processor; the radio controller and the packet manager. The radio controller manages the state of the IC in various operating modes and configurations. The host MCU can use single byte commands to interface to the radio controller. The packet manager is highly flexible and supports various packet formats. In transmit mode, the packet manager can be confi- gured to add preamble, sync, and CRC words to the payload data stored in the on-chip packet RAM. In receive mode, the packet manager can detect and generate an interrupt to the MCU upon receiving valid sync or CRC words, and store the received data payload in the packet RAM. A total of 256 bytes of transmit and receive packet RAM space is provided to decouple the over-the-air data rate from the host MCU processing speed. Thus, the ADF7242 packet manager eases the processing burden on the host MCU and saves the overall system power consumption. In addition, for applications that require data streaming, a synchronous bidirectional serial port (SPORT) provides bit- level input/output data, and has been designed to directly inter- face to a wide range of DSPs, such as ADSP-21xx, SHARC®, TigerSHARC®, and Blackfin®. The SPORT interface can option- ally be used for GFSK/FSK as well as IEEE 802.15.4-2006 modes. The processor also permits the download and execution of a set of firmware modules, which include IEEE 802.15.4 automatic modes, such as node address filtering, as well as unslotted CSMA/CA. Execution code for these firmware modules is available from Analog Devices, Inc. To further optimize the system power consumption, the ADF7242 features an integrated low power 32 kHz RC wake-up oscillator, which is calibrated from the 26 MHz crystal oscillator while the transceiver is active. Alternatively, an integrated 32 kHz crystal oscillator can be used as a wake-up timer for applications requiring very accurate wake-up timing. A battery backed-up RAM (BBRAM) is available on the IC where IEEE 802.15.4- 2006 network node addresses can be retained when the IC is in the sleep state. The ADF7242 also features a very flexible interrupt controller, which provides MAC-level and PHY-level interrupts to the host MCU. The IC is equipped with a SPI interface, which allows burst-mode data transfer for high data throughput efficiency. The IC also integrates a temperature sensor with digital read- back and a battery monitor. |
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