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KM4132G271AQ-10 Scheda tecnica(PDF) 7 Page - Samsung semiconductor

Il numero della parte KM4132G271AQ-10
Spiegazioni elettronici  128K x 32Bit x 2 Banks Synchronous Graphic RAM
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Produttore elettronici  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

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KM4132G271A
CMOS SGRAM
Rev.0 (August 1997)
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-8
-10
-12
Row active to row active delay
tRRD(min)
16
20
24
ns
1
RAS to CAS delay
tRCD(min)
16
20
24
ns
1
Row precharge time
tRP(min)
24
26
30
ns
1
Row active time
tRAS(min)
48
50
60
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
80
80
90
ns
1
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to row precharge
tRDL(min)
1
CLK
2
Block write data-in to PRE command delay
tBPL(min)
16
20
24
ns
Block write data-in to Active(REF)
command period(Auto precharge)
tBAL(min)
40
46
54
ns
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Block write cycle time
tBWC(min)
16
20
24
ns
1, 4
Number of valid output data
CAS Latency=3
2
CLK
5
CAS Latency=2
1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change except block write cycle.
4. This parameter means minimum CAS to CAS delay at block write cycle only.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Note :


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