KM4132G271A-12 datasheet(9/48 Pages) SAMSUNG

Il numero della parte	KM4132G271A-12

Spiegazioni elettronici	128K x 32Bit x 2 Banks Synchronous Graphic RAM

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Produttore elettronici	SAMSUNG [Samsung semiconductor]

Homepage	http://www.samsung.com/Products/Semiconductor

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KM4132G271A

CMOS SGRAM

Rev.0 (August 1997)

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don't Care, H=Logic High, L=Logic Low)

COMMAND

CKEn-1 CKEn

CS

RAS

CAS

WE

DSF

DQM

A9

A8

A7~ A0

Note

Register

Mode Register Set

H

X

L

X

OP CODE

1, 2

Special Mode Register Set

H

1,2,7

Refresh

Auto Refresh

H

L

H

L

X

3

Self

Refresh

Entry

L

3

Exit

L

H

L

H

X

3

H

X

3

Bank Active

& Row Addr.

Write Per Bit Disable

H

X

L

H

L

X

V

Row Address

4, 5

Write Per Bit Enable

H

4,5,9

Read &

Column Address

Auto Precharge Disable

H

X

L

H

L

H

L

X

V

L

Column

Address

4

Auto Precharge Enable

H

4, 6

Write &

Column Address

Auto Precharge Disable

H

X

L

H

L

X

V

L

Column

Address

4, 5

Auto Precharge Enable

H

4,5,6,9

Block Write &

Column Addr.

Auto Precharge Disable

H

X

L

H

L

H

X

V

L

Column

Address

4, 5

Auto Precharge Enable

H

4,5,6,9

Burst Stop

H

X

L

H

L

X

7

Precharge

Bank Selection

H

X

L

H

L

X

V

L

X

Both Banks

X

H

Clock Suspend or

Active Power Down

Entry

H

L

H

X

H

X

Exit

L

H

X

Precharge Power Down Mode

Entry

H

L

H

X

H

X

Exit

L

H

L

V

X

H

X

DQM

H

X

V

X

8

No Operation Command

H

X

L

H

X

H

X

1. OP Code : Operand Code

A0 ~ A9 : Program keys. (@MRS)

A5, A6 : LMR or LCR select. (@SMRS)

Color register exists only one per DQi which both banks share.

So dose Mask Register.

Color or mask is loaded into chip through DQ pin.

2. MRS can be issued only at both banks precharge state.

SMRS can be issued only if DQ's are idle.

A new command can be issued at the next clock of MRS/SMRS.

Note :

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