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BU2879AK Scheda tecnica(PDF) 3 Page - Rohm |
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BU2879AK Scheda tecnica(HTML) 3 Page - Rohm |
3 / 5 page 3 Standard ICs BU2879AK •Pins descriptions Pin No. Pin Name I / O Function 14, 38 VDD Power supply pin 1 Oscillation pin Ground pin Input Input / output Input Connected to system power supply. OSC Capacitor connection pin for oscillation 44 VSS Connected to system ground. 7, 43 Serial data input Input SI Serial data input starting from MSB 6 Serial clock input Input SCK Serial data read at rising edge. 8 Serial chip select Input CS Serial initialization when LOW, valid at HIGH. 9 High-voltage withstand Output pin for segment; output is output pin for segment Output Pch open drain + pull-down resistance. S1 ~ S11 15 ~ 25 Power supply pin 2 Input VEE Pull-down resistance connection for FLP driver output. 27 High-voltage withstand Output pin for grid; output is Pch output pin for grid Output open drain + pull-down resistance. G1 ~ G10 42 ~ 39, 37 ~ 32 High-voltage withstand S12 / G15 Used to switch output between segment and grid; 26, output pin for segment / grid Output output is Pch open drain + pull-down resistance. S16 / G11 28 ~ 31 Key data input pin Data input pin for key scanning. Input K1 ~ K4 10 ~ 13 General-purpose input pin; input data can be General-purpose input pin Input transmitted serially to microcomputer. SW1 ~ SW4 1 ~ 4 Serial data output Output SO Serial data output starting from MSB; output is Nch open drain. 5 •Electrical characteristics (unless otherwise noted, Ta = 25°C, VDD = 5V, VSS = 0V, VDD – VEE = 35V) Parameter Symbol Conditions IDD Supply current 44-pin attachment, at 1000pF oscillation VIN Input threshold voltage Pins 1 to 4, 6, 8, 9 to 13 IIN Input current Pins 1 to 4, 6, 8, 9 to 13 FOSC OSC oscillation frequency 44-pin attachment, at 1000pF oscillation IOseg Segment output current Pins 15 to 26, 28 to 31, VO = VDD – 2V∗ IOgrd Grid output current Pins 26, 28 to 37, 39 to 42, VO = VDD – 2V∗ IOFF Leakage current when OFF Pins 15 to 26, 28 to 37, VO = VDD – VEE RD Output pull-down resistance Pins 15 to 26, 28 to 37 FMAX Maximum operating frequency Design guarantee value 〈Serial transmission〉 TSH Input data hold TSS Input data setup TD Output data delay TSCYC Input clock cycle TSW Input clock "H" width Min. — 1.5 — 130 6 18 — 35 — 0.16 0.16 — 0.5 40 Typ. — — — 200 — — — 70 — — — — — — Max. 5 3.5 10 300 — — 10 140 1 — — 0.3 — 60 Unit mA V µA kHz mA mA µA k Ω MHz µs µs µs µs % At minimum input clock cycle Measurement circuit Fig.1 Fig.4 Fig.2 Fig.3 Fig.2 Fig.2 Fig.2 Fig.2 Fig.3 — — — — — — — — — ∗ For the high voltage withstand output pins for the segment / grid of pins 26 and 28 to 31, when segment output is specified, segment output current is output, and when grid output is specified, grid current is output. |
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