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LMZ14201 Scheda tecnica(PDF) 11 Page - National Semiconductor (TI) |
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LMZ14201 Scheda tecnica(HTML) 11 Page - National Semiconductor (TI) |
11 / 18 page abled. This implements the feature of programmable under voltage lockout. This is often used in battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for sequencing of output rails or to prevent early turn-on of the supply as the main input voltage rail rises at power-up. Applying the enable divider to the main input rail is often done in the case of higher input voltage sys- tems such as 24V AC/DC systems where a lower boundary of operation should be established. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ14201 output rail. The two resistors should be chosen based on the following ratio: R ENT / RENB = (VIN UVLO/ 1.18V) – 1 (1) The LMZ14201 demonstration and evaluation boards use 11.8k Ω for R ENB and 68.1kΩ for RENT resulting in a rising UV- LO of 8V. This divider presents 6.25V to the EN input when the divider input is raised to 42V. The EN pin is internally pulled up to VIN and can be left float- ing for always-on operation. OUTPUT VOLTAGE SELECTION Output voltage is determined by a divider of two resistors connected between V O and ground. The midpoint of the di- vider is connected to the FB input. The voltage at FB is compared to a 0.8V internal reference. In normal operation an on-time cycle is initiated when the voltage on the FB pin falls below 0.8V. The main MOSFET on-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8V. As long as the voltage at FB is above 0.8V, on-time cycles will not occur. The regulated output voltage determined by the external di- vider resistors RFBT and RFBB is: V O = 0.8V * (1 + RFBT / RFBB) (2) Rearranging terms; the ratio of the feedback resistors for a desired output voltage is: R FBT / RFBB = (VO / 0.8V) - 1 (3) These resistors should be chosen from values in the range of 1.0 kohm to 10.0 kohm. For V O = 0.8V the FB pin can be connected to the output di- rectly so long as an output preload resistor remains that draws more than 20uA. Converter operation requires this minimum load to create a small inductor ripple current and maintain proper regulation when no load is present. A feed-forward capacitor is placed in parallel with R FBT to im- prove load step transient response. Its value is usually deter- mined experimentally by load stepping between DCM and CCM conduction modes and adjusting for best transient re- sponse and minimum output ripple. A table of values for R FBT , RFBB , CFF and RON is included in the applications schematic. SOFT-START CAPACITOR SELECTION Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot. Upon turn-on, after all UVLO conditions have been passed, an internal 8uA current source begins charging the external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula: t SS = VREF * CSS / Iss = 0.8V * CSS / 8uA (4) This equation can be rearranged as follows: C SS = tSS * 8 μA / 0.8V (5) Use of a 0.022 μF results in 2.2 msec soft-start interval which is recommended as a minimum value. As the soft-start input exceeds 0.8V the output of the power stage will be in regulation. The soft-start capacitor continues charging until it reaches approximately 3.8V on the SS pin. Voltage levels between 0.8V and 3.8V have no effect on other circuit operation. Note that the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal 200 μA current sink. • The enable input being “pulled low” • Thermal shutdown condition • Over-current fault • Internal Vcc UVLO (Approximately 4V input to V IN) C O SELECTION None of the required C O output capacitance is contained with- in the module. At a minimum, the output capacitor must meet the worst case minimum ripple current rating of 0.5 * I LR P-P, as calculated in equation (19) below. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF is generally required. Experimentation will be required if attempting to op- erate with a minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 for more detail. The following equation provides a good first pass approxima- tion of C O for load transient requirements: C O≥ISTEP*VFB*L*VIN/ (4*VO*(VIN—VO)*VOUT-TRAN)(6) Solving: C O≥ 1A*0.8V*10μH*24V / (4*3.3V*( 24V — 3.3V)*33mV) ≥ 21.3μF (7) The LMZ14201 demonstration and evaluation boards are populated with a 100 uF 6.3V X5R output capacitor. Locations for other output capacitors are provided. C IN SELECTION The LMZ14201 module contains an internal 0.47 µF input ce- ramic capacitor. Additional input capacitance is required ex- ternal to the module to handle the input ripple current of the application. This input capacitance should be located in very close proximity to the module. Input capacitor selection is generally directed to satisfy the input ripple current require- ments rather than by capacitance value. Worst case input ripple current rating is dictated by the equation: I(C IN(RMS)) ≊ 1 /2 * IO * √ (D / 1-D) (8) where D ≊ V O / VIN (As a point of reference, the worst case ripple current will oc- cur when the module is presented with full load current and when V IN = 2 * VO). Recommended minimum input capacitance is 10uF X7R ce- ramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. It is also recommended that attention be paid to the voltage and tem- perature deratings of the capacitor selected. It should be noted that ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating. If the system design requires a certain minimum value of input ripple voltage ΔV IN be maintained then the following equation may be used. C IN ≥ IO * D * (1–D) / fSW-CCM * ΔVIN(9) 11 www.national.com |
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