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AM1808_1008 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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AM1808_1008 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 264 page AM1808 www.ti.com SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 Table 3-1. Characteristics of the device (continued) HARDWARE FEATURES AM1808 Product Preview (PP), Product Status(1) Advance Information (AI), AI or Production Data (PD) (1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. 3.2 Device Compatibility The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. 3.3 ARM Subsystem The ARM Subsystem includes the following features: • ARM926EJ-S RISC processor • ARMv5TEJ (32/16-bit) instruction set • Little endian • System Control Co-Processor 15 (CP15) • MMU • 16KB Instruction cache • 16KB Data cache • Write Buffer • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) • ARM Interrupt controller 3.3.1 ARM926EJ-S RISC CPU The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including: • ARM926EJ -S integer core • CP15 system control coprocessor • Memory Management Unit (MMU) • Separate instruction and data caches • Write buffer • Separate instruction and data (internal RAM) interfaces • Separate instruction and data AHB bus interfaces • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com Copyright © 2010, Texas Instruments Incorporated Device Overview 9 Submit Documentation Feedback Product Folder Link(s): AM1808 |
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