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MC14LC5003FU Scheda tecnica(PDF) 10 Page - Motorola, Inc |
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MC14LC5003FU Scheda tecnica(HTML) 10 Page - Motorola, Inc |
10 / 17 page MOTOROLA 3–12 MC14LC5002 • MC14LC5003 • MC14LC5004 DATA INPUT PROTOCOL Two-wire communication bus DCLK, Din; three-wire com- munication bus DCLK, Din, ENB. MC14LC5002/5003 — SERIAL INTERFACE DEVICE (FIG- URE 7) Before communication with an MC14LC5002/5003 can be- gin, a start condition must be set up on the bus by the trans- mitter. To establish a start condition, the transmitter must pull the data line low for at least one clock-pulse time while the clock line is high. The “idle” state for the clock line and data line is the high state. After the start condition has been established, an eight-bit address (01111110) should be sent by the transmitter. If the address sent corresponds to the address of the MC14LC5002/5003 then on each successive clock pulse, the addressed device will accept a data bit. If the ENB pin is permanently high, then the addressed MC14LC5002/5003’s internal counter latches the data to be displayed after 128 data bits have been received. Otherwise, the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC14LC5002/5003, a stop condition should be set up on the bus (or another start con- dition may be set up if another communication is desired). To establish a stop condition, the transmitter must pull the data line high for at least one clock-pulse time while the clock line is high. Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case, the 129th rising DCLK edge, which normally would be used to set up the stop or start condition, is ignored by the MC14LC5002/5003 and data continues to be received on the 130th rising DCLK. The latch function continues to work as normal (i.e., data is be latched either after each block of 128 data bits has been received or under external control as re- quired). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. MC14LC5004 — IIC DEVICE (FIGURE 8) Before communication with an MC14LC5004 can begin, a start condition must be set up on the bus by the controller. To establish a start condition, the controller must pull the data line low for at least one clock-pulse time while the clock line is high. After the start condition has been established, an eight-bit address (0111111X0) should be sent by the controller followed by an extra clock pulse while the data line is left high. In this option, only the seven most significant bits of the address are used to uniquely define devices on the bus, the least significant bit X0 is used as a read/write control: if the least significant bit is 0, then the controller writes to the LCD driver; if it is 1, then the controller reads from the LCD driver’s 128-bit shift register on a first-in first-out basis. If the seven most significant address bits sent correspond to the address of the LCD driver then the addressed LCD driver responds by sending an “acknowledge” bit back to the controller (i.e., the LCD driver pulls the data line low during the extra clock pulse supplied by the controller). If the least significant address bit was 0, then the controller should continue to send data to the LCD driver in blocks of eight bits followed by an extra ninth clock pulse to allow the LCD driver to pull the data line Din low as an acknowledgment. If the least significant address bit was 1, then the LCD driver sends data back to the controller (the clock is supplied by the controller). After each successive group of eight bits sent, the LCD driver leaves the data line high for one pulse. If the ENB pin is permanently high, then the addressed MC14LC5004’s internal counter latches the data to be dis- played after 128 data bits have been received. Otherwise the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC14LC5004, a stop condi- tion should be set up on the bus (or another start condition may be set up if another communication is desired). To estab- lish a stop condition, the transmitter must pull the data line high for at least one clock-pulse time while the clock line is high. Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case the rising DCLK edge which comes after all 128 data bits have been sent and after the last acknowledge-related clock pulse has been made is ignored; data continues to be received on the following DCLK high. The latch function continues to work as normal (i.e., data is latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. |
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