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i.MX27L Scheda tecnica(PDF) 9 Page - Freescale Semiconductor, Inc |
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i.MX27L Scheda tecnica(HTML) 9 Page - Freescale Semiconductor, Inc |
9 / 148 page i.MX27 and i.MX27L Data Sheet, Rev. 1.5 Freescale Semiconductor 9 Functional Description and Application Information 2.3 Module Descriptions This section provides a brief text description of all the modules included in the i.MX27/MX27L devices, arranged in alphabetical order. 2.3.1 1-Wire Module The 1-Wire module provides bi-directional communication between the ARM926 core and the Add-Only Memory EPROM, DS2502. The 1-Kbit EPROM holds information about the battery and communicates with the ARM926 Platform using the IP interface. Through the 1-Wire interface, the ARM926 acts as the bus master while the DS2502 device is the slave. The 1-Wire peripheral does not trigger interrupts; hence it is necessary for the ARM926 to poll the 1-Wire to manage the module. The 1-Wire uses an external pin to connect to the DS2502. Timing requirements are met in hardware with the help of a 1 MHz clock. The clock divider generates a 1 MHz clock that is used as a time reference by the state machine. Timing requirements are crucial for proper operation, and the 1-Wire state machine and the internal clock provide the necessary signal. The clock must be configured to approximately 1 MHz. You can then set the 1-Wire register to send and receive bits over the 1-Wire bus. USB Universal Serial Bus–2 Host Controllers and 1 OTG (On-The-Go) Connectivity Peripherals The i.MX27/MX27L processors provide two USB Host controllers and one USBOTG of which: • USB Host 1 is designed to support transceiverless connection to the on-board peripherals in Low Speed and Full Speed mode, and connection to the ULPI (UTMI+Low-Pin Court) and Legacy Full Speed transceivers • USB Host 2 is designed to support transceiverless connection to the Cellular Modem Baseband Processor • The USBOTG controller offers HS/FS/LS capabilities in Host mode and HS/FS in device mode. In Host mode, the controller supports direct connection of a FS/LS device (without external hub). In device (bypass) mode, the OTG port functions as gateway between the Host 1 Port and the OTG transceiver. 2.3.36/23 Video Codec Video Codec Hardware Acceleration Video Codec module supports full duplex video codec with 25 fps VGA image resolution, integrates H.264 BP, MPEG-4 SP and H.263 P3 video processing standard together. 2.3.39/25 WDOG Watchdog Timer Module Timer Peripheral The WDOG module protects against system failures by providing a method for the system to recover from unexpected events or programming errors. 2.3.37/24 WEIM Wireless External Interface Module External Memory Interface The Wireless External Module (WEIM) handles the interface to devices external to chip, including generation of chip selects, clock and control for external peripherals and memory. It provides asynchronous and synchronous access to devices with SRAM-like interface. 2.3.38/25 Table 2. Digital and Analog Modules (continued) Block Mnemonic Block Name Functional Grouping Brief Description Section/ Page |
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