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74ABT652APW Scheda tecnica(PDF) 5 Page - NXP Semiconductors |
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74ABT652APW Scheda tecnica(HTML) 5 Page - NXP Semiconductors |
5 / 19 page 74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 12 March 2010 5 of 19 NXP Semiconductors 74ABT652A Octal transceiver/register; non-inverting; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 5. Pin configuration 74ABT652A CPAB VCC SAB CPBA OEAB SBA A0 OEBA A1 B0 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 GND B7 001aae844 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 Table 2. Pin description Symbol Pin Description CPAB 1 A to B clock input SAB 2 A to B select input OEAB 3 A to B output enable input A0, A1, A2, A3, A4, A5, A6, A7 4, 5, 6, 7, 8, 9, 10, 11 data input/output (A side) GND 12 ground (0 V) B0, B1, B2, B3, B4, B5, B6, B7 20, 19, 18, 17, 16, 15, 14, 13 data input/output (B side) OEBA 21 B to A output enable input (active LOW) SBA 22 B to A select input CPBA 23 B to A clock input VCC 24 positive supply voltage |
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