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74ABT543AD Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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74ABT543AD Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 15 page 74ABT543A_3 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 26 January 2010 9 of 15 NXP Semiconductors 74ABT543A Octal latched transceiver with dual enable; 3-state VM = 1.5 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times and latch enable pulse width 001aae905 VM An, Bn LEAB, LEBA, EAB, EBA VM VM VM VM VM tsu(H) th(H) tsu(L) th(L) tWL VI GND VI GND a. Input pulse definition b. Test circuit Test data is given in Table 8. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 10. Load circuitry for switching times 001aac221 VM VM tW tW 10 % 90 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % 10 % tf tr tr tf VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 8. Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V |
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