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TS16GSSD25S-M Scheda tecnica(PDF) 8 Page - Transcend Information. Inc. |
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TS16GSSD25S-M Scheda tecnica(HTML) 8 Page - Transcend Information. Inc. |
8 / 38 page T T TS S S8 8 8G G GS S SS S SD D D2 2 25 5 5S S S---S S S T T TS S S1 1 16 6 6G G GS S SS S SD D D2 2 25 5 5S S S---S S S///M M M T T TS S S3 3 32 2 2G G GS S SS S SD D D2 2 25 5 5S S S---S S S///M M M T T TS S S6 6 64 4 4G G GS S SS S SD D D2 2 25 5 5S S S---S S S///M M M T T TS S S1 1 12 2 28 8 8G G GS S SS S SD D D2 2 25 5 5S S S---M M M T T TS S S1 1 19 9 92 2 2G G GS S SS S SD D D2 2 25 5 5S S S---M M M 2.5” Solid State Disk Transcend Information Inc. V2.4 8 Reliability Wear-Leveling algorithm The controller supports static/dynamic wear leveling. When the host writes data, the controller will find and use the block with the lowest erase count among the free blocks. This is known as dynamic wear leveling. When the free blocks' erase count is higher than the data blocks', it will activate the static wear leveling, replacing the not so frequently used user blocks with the high erase count free blocks. ECC algorithm The controller uses BCH8/BCH15 ECC algorithm per 512 bytes. BCH8/BCH15 can correct up to 8 or 15 random error bits within 512 data bytes. Bad-block management When the flash encounters ECC failed, program fail or erase fail, the controller will mark the block as bad block to prevent the used of this block and caused data lost later on. |
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