74HC125

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2

LOGIC DIAGRAM

HC125

Active−Low Output Enables

Y1

Y2

Y4

3

6

8

11

13

12

10

9

4

5

1

2

A1

OE1

A2

OE2

A3

OE3

A4

OE4

PIN 7 = GND

Y3

FUNCTION TABLE

HC125

Inputs

Output

AOE

Y

HL

H

LL

L

XH

Z

PIN ASSIGNMENT

11

12

13

14

8

9

10

5

4

3

2

1

7

6

OE3

Y4

A4

OE4

Y3

A3

OE2

Y1

A1

OE1

GND

Y2

A2

MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

V

DC Output Voltage (Referenced to GND)

V

DC Input Current, per Pin

±20

mA

DC Output Current, per Pin

±35

mA

±75

mA

Power Dissipation in Still Air

SOIC Package†

TSSOP Package†

500

450

mW

Storage Temperature

– 65 to + 150

_C

Lead Temperature, 1 mm from Case for 10 Seconds

(SOIC or TSSOP Package)

260

_C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device

reliability.

†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

Unused inputs must always be

tied to an appropriate logic voltage

Unused outputs must be left open.