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5V50017DCG8 Scheda tecnica(PDF) 2 Page - Integrated Device Technology |
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2 / 8 page IDT5V50017 LOW EMI CLOCK GENERATOR SSCG IDT™ LOW EMI CLOCK GENERATOR 2 IDT5V50017 REV D 040709 Pin Assignment Spread Direction and Percentage Select Table 0 = connect to GND 1 = connect directly to VDD Pin Descriptions ICLK VDD GND S0 SSCLK S1 GND VDD 1 2 3 4 8 7 6 5 8 pin (150 mil) SOIC S1 Pin 6 S0 Pin 7 Spread Direction Spread Percentage 00 OFF - 01 Down -1.0% 10 Down -2.0% 11 Down -3.0% Pin Number Pin Name Pin Type Pin Description 1 ICLK Input 15-60 MHz clock input. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 SSCLK Output Clock output with spread spectrum. 5 GND Power Connect to ground. 6 S1 Input Function select 1 input. Selects spread amount and direction per table above. Internal pull-down. 7 S0 Input Function select 0 input. Selects spread amount and direction per table above. Internal pull-down. 8 VDD Power Connect to +3.3 V. |
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