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SM59D04G2 Scheda tecnica(PDF) 6 Page - SyncMOS Technologies,Inc |
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SM59D04G2 Scheda tecnica(HTML) 6 Page - SyncMOS Technologies,Inc |
6 / 67 page SM59D04G2 8-Bits Micro-controller 16KB+ ISP Flash & 1KB RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M031 6 Ver.C SM59D04G2 07/2009 Pin Description 40L PDIP Pin# 44L QFP Pin# 44L PLCC Pin# Symbol I/O Names 1 40 2 P10/T2/EEI0/ICP_CLK i/o Bit 0 of port 1 & Timer 2 external input clock & EEI interrupt 0 & ICP clock input 2 41 3 P11/T2EX/EEI1/ICP_TRIG i/o Bit 1 of port 1 & Timer 2 capture trigger & EEI interrupt 1 & ICP Trigger (active low) 3 42 4 P12/CCCI/EEI2 /ICP_DATA i/o Bit 2 of port 1 & PCA External clock input & EEI interrupt 2 & ICP data/command IO 4 43 5 P13/CC0/EEI3 i/o Bit 3 of port 1 & PCA Channel 0 & EEI interrupt 3 5 44 6 P14/CC1/EEI4 i/o Bit 4 of port 1 & PCA Channel 1 & EEI interrupt 4 6 1 7 P15/CC2/EEI5 i/o Bit 5 of port 1 & PCA Channel 2 & EEI interrupt 5 7 2 8 P16/CC3/EEI6 i/o Bit 6 of port 1 & PCA Channel 3 & EEI interrupt 6 8 3 9 P17/CC4/EEI7 i/o Bit 7 of port 1 & PCA Channel 4 & EEI interrupt 7 9 4 10 RESET i Hardware reset input (active high) 10 5 11 P30/RXD i/o Bit 0 of port 3 & Serial interface channel receive/transmit data 11 7 13 P31/TXD i/o Bit 1 of port 3 & Serial interface channel transmit data or receive clock in mode 0 12 8 14 P32/INT0 i/o Bit 2 of port 3 & External interrupt 0 (low or falling-edge trigger) 13 9 15 P33/INT1 i/o Bit 3 of port 3 & External interrupt 1 (low or falling-edge trigger) 14 10 16 P34/T0 i/o Bit 4 of port 3 & Timer 0 external input 15 11 17 P35/T1 i/o Bit 5 of port 3 & Timer 1 external input 16 12 18 P36/WR i/o Bit 6 of port 3 & external memory write signal 17 13 19 P37/RD i/o Bit 7 of port 3 & external memory read signal 18 14 20 XTAL2 o Crystal output or oscillator input 19 15 21 XTAL1 i Crystal input 20 16 22 VSS Ground 21 18 24 P20/A8 i/o Bit 0 of port 2 & Bit 8 of external memory address 22 19 25 P21/A9 i/o Bit 1 of port 2 & Bit 9 of external memory address 23 20 26 P22/A10 i/o Bit 2 of port 2 & Bit 10 of external memory address 24 21 27 P23/A11 i/o Bit 3 of port 2 & Bit 11 of external memory address 25 22 28 P24/A12 i/o Bit 4 of port 2 & Bit 12 of external memory address 26 23 29 P25/A13 i/o Bit 5 of port 2 & Bit 13 of external memory address 27 24 30 P26/A14 i/o Bit 6 of port 2 & Bit 14 of external memory address 28 25 31 P27/A15 i/o Bit 7 of port 2 & Bit 15 of external memory address 29 26 32 PSEN/ Clk_out o Program storage enable (active low) & crystal/oscillator clock output as the clock source for the others 30 27 33 ALE o Address latch enable 31 29 35 EA I External access with internal pull-up (active low) 32 30 36 P07/AD7 i/o Bit 7 of port 0 & Bit 7 of external memory address/data 33 31 37 P06/AD6 i/o Bit 6 of port 0 & Bit 6 of external memory address/data 34 32 38 P05/AD5 i/o Bit 5 of port 0 & Bit 5 of external memory address/data 35 33 39 P04/AD4 i/o Bit 4 of port 0 & Bit 4 of external memory address/data 36 34 40 P03/AD3 i/o Bit 3 of port 0 & Bit 3 of external memory address/data 37 35 41 P02/AD2 i/o Bit 2 of port 0 & Bit 2 of external memory address/data 38 36 42 P01/AD1 i/o Bit 1 of port 0 & Bit 1 of external memory address/data 39 37 43 P00/AD0 i/o Bit 0 of port 0 & Bit 0 of external memory address/data 40 38 44 VDD Power supply 17 23 P40 i/o Bit 0 of port 4 28 34 P41 i/o Bit 1 of port 4 39 1 P42 i/o Bit 2 of port 4 6 12 P43 i/o Bit 3 of port 4 |
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