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FDG1024NZ Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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FDG1024NZ Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 ©2009 Fairchild Semiconductor Corporation FDG1024NZ Rev.B Electrical Characteristics T J = 25 °C unless otherwise noted Off Characteristics On Characteristics Dynamic Characteristics Switching Characteristics Drain-Source Diode Characteristics Symbol Parameter Test Conditions Min Typ Max Units BVDSS Drain to Source Breakdown Voltage ID = 250 µA, VGS = 0 V 20 V ∆BV DSS ∆T J Breakdown Voltage Temperature Coefficient ID = 250 µA, referenced to 25 °C 14 mV/°C IDSS Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V 1 µA IGSS Gate to Source Leakage Current VGS = ±8 V, VDS = 0 V ±10 µA VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 µA 0.4 0.8 1.0 V ∆V GS(th) ∆T J Gate to Source Threshold Voltage Temperature Coefficient ID = 250 µA, referenced to 25 °C -3 mV/°C rDS(on) Static Drain to Source On Resistance VGS = 4.5 V, ID = 1.2 A 160 175 m Ω VGS = 2.5 V, ID = 1.0 A 185 215 VGS = 1.8 V, ID = 0.9 A 232 270 VGS = 1.5 V, ID = 0.8 A 321 389 VGS = 4.5 V, ID = 1.2 A, TJ =125 °C 220 259 gFS Forward Transconductance VDD = 5 V, ID = 1.2 A 4 S Ciss Input Capacitance VDS = 10 V, VGS = 0 V, f = 1 MHz 115 150 pF Coss Output Capacitance 25 35 pF Crss Reverse Transfer Capacitance 20 25 pF Rg Gate Resistance 4.6 Ω td(on) Turn-On Delay Time VDD = 10 V, ID = 1.2 A, VGS = 4.5 V, RGEN = 6 Ω 3.7 10 ns tr Rise Time 1.7 10 ns td(off) Turn-Off Delay Time 11 19 ns tf Fall Time 1.5 10 ns Qg Total Gate Charge VGS = 4.5 V, VDD = 10 V, ID = 1.2 A 1.8 2.6 nC Qgs Gate to Source Charge 0.3 nC Qgd Gate to Drain “Miller” Charge 0.4 nC IS Maximum Continuous Drain-Source Diode Forward Current 0.3 A VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 0.3 A (Note 2) 0.7 1.2 V trr Reverse Recovery Time IF = 1.2 A, di/dt = 100 A/µs 10 20 ns Qrr Reverse Recovery Charge 1.9 10 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθJA is determined by the user's board design. 2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3: The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. a. 350 °C/W when mounted on a 1 in2 pad of 2 oz copper. b. 415 °C/W when mounted on a minimum pad of 2 oz copper. |
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