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FDG1024NZ Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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FDG1024NZ Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page ©2009 Fairchild Semiconductor Corporation FDG1024NZ Rev.B www.fairchildsemi.com 1 August 2009 S1 SC70-6 S1 G1 D2 D1 G2 S2 G1 D2 D1 G2 S2 3 2 1 4 5 6 FDG1024NZ Dual N-Channel PowerTrench® MOSFET 20 V, 1.2 A, 175 m Ω Features Max rDS(on) = 175 mΩ at VGS = 4.5 V, ID = 1.2 A Max rDS(on) = 215 mΩ at VGS = 2.5 V, ID = 1.0 A Max rDS(on) = 270 mΩ at VGS = 1.8 V, ID = 0.9 A Max rDS(on) = 389 mΩ at VGS = 1.5 V, ID = 0.8 A HBM ESD protection level >2 kV (Note 3) Very low level gate drive requirements allowing operation in 3 V circuits (VGS(th) < 1.5 V) Very small package outline SC70-6 RoHS Compliant General Description This dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values. MOSFET Maximum Ratings T A = 25 °C unless otherwise noted Thermal Characteristics Package Marking and Ordering Information Symbol Parameter Ratings Units VDS Drain to Source Voltage 20 V VGS Gate to Source Voltage ±8 V ID -Continuous TA = 25°C (Note 1a) 1.2 A -Pulsed 6 PD Power Dissipation TA = 25°C (Note 1a) 0.36 W Power Dissipation TA = 25°C (Note 1b) 0.30 TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C RθJA Thermal Resistance, Junction to Ambient (Note 1a) 350 °C/W RθJA Thermal Resistance, Junction to Ambient (Note 1b) 415 Device Marking Device Package Reel Size Tape Width Quantity .24 FDG1024NZ SC70-6 7 ” 8 mm 3000 units |
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