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FDG1024NZ Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor |
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FDG1024NZ Scheda tecnica(HTML) 4 Page - Fairchild Semiconductor |
4 / 7 page www.fairchildsemi.com 4 ©2009 Fairchild Semiconductor Corporation FDG1024NZ Rev.B Figure 7. 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 Qg, GATE CHARGE (nC) ID = 1.2 A VDD = 10 V VDD = 5 V VDD = 15 V Gate Charge Characteristics Figure 8. 0.1 1 10 20 5 10 100 300 f = 1 MHz VGS = 0 V VDS, DRAIN TO SOURCE VOLTAGE (V) Crss Coss Ciss Capacitance vs Drain to Source Voltage Figure 9. 0.01 0.1 1 10 100 0.01 0.1 1 10 0.1 ms 10 ms DC 1 s 100 ms 1 ms VDS, DRAIN to SOURCE VOLTAGE (V) THIS AREA IS LIMITED BY r DS(on) SINGLE PULSE TJ = MAX RATED RθJA = 415 oC/W TA = 25 oC Forward Bias Safe Operating Area Figure 10. 0246 8 10 12 14 10 -3 10 -1 10 10 3 10 5 VGS = 0 V TJ = 25 oC TJ = 125 oC VGS, GATE TO SOURCE VOLTAGE (V) Gate Leakage Current vs Gate to Source Voltage Figure 11. Single Pulse Maximum Power Dissipation 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 V GS = 4.5 V t, PULSE WIDTH (sec) SINGLE PULSE RθJA = 415 oC/W TA = 25 oC Typical Characteristics T J = 25 °C unless otherwise noted |
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