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UC1725 Scheda tecnica(PDF) 3 Page - Texas Instruments

Il numero della parte UC1725
Spiegazioni elettronici  Isolated High Side FET Driver
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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UC1725 Scheda tecnica(HTML) 3 Page - Texas Instruments

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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ENABLE SECTION (PIN 6)
High Level Input Voltage
2.1
1.4
V
Low Level Input Voltage
1.4
.8
V
Input Bias Current
-250
-500
µA
OUTPUT SECTION
Output Low Level
IOUT = 20mA
0.35
0.5
V
IOUT = 200mA
0.6
2.5
V
Output High Level
IOUT = -20mA
13
13.5
V
IOUT = -200mA
12
13.4
V
VCC = 30V, Iout = -20mA
14
15
V
Rise/Fall Time
CT = 1nf
30
60
ns
UNDER VOLTAGE LOCKOUT
UVLO Low Saturation
20mA, VCC = 8V
0.8
1.5
V
Start-up Threshold
11.2
12
12.6
V
Threshold Hysteresis
.75
1.0
1.12
V
TOTAL STANDBY CURRENT
Supply Current
12
16
ma
UC1725
UC2725
UC3725
ELECTRICAL
CHARACTERISTICS (cont.)
(Unless otherwise stated, these specifications apply for -55
°C≤TA≤+125°C for UC1725;
-25
°C≤TA≤+85°C for UC2725; 0°C≤TA≤+70°C for UC3725; VCC (pin 3) = 0 to 15V, Rt=10k,
CT=2.2nf, TA =TJ, pin numbers refer to DIL-8 package.)
INPUTS: Figure 1 shows the rectification and detection
scheme used in the UC1725 to derive both power and
signal information from the input waveform. Vcc is gener-
ated by peak detecting the input signal via the internal
bridge rectifier and storing on a small external capacitor,
C1. Note that this capacitor is also used to bypass high
pulse currents in the output stage, and therefore should
be placed direclty between pins 1 and 3 using minimal
lead lengths.
Signal detection is performed by the internal hysteresis
comparator which senses the polarity of the input signal
as shown in Figure 2. This is accomplished by setting
(resetting) the comparator only if the input signal ex-
ceeds Vcc (-Vcc). In some cases it may be necessary to
add a damping resistor across the transformer secondary
to minimize ringing and eliminate false triggering of the
hysteresis amplifier as shown in Figure 3.
APPLICATION AND OPERATION INFORMATION
FIGURE 1 - Input Stage
FIGURE 2 - Input Waveform (DIL-8 Pin 7 - Pin 8)
FIGURE 3 - Signal Detection
UDG-92047
UDG-92048
UDG-92049
3


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