Motore di ricerca datesheet componenti elettronici |
|
UC1633 Scheda tecnica(PDF) 1 Page - Texas Instruments |
|
UC1633 Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 8 page 4/97 • Precision Phase Locked Frequency Control System • Crystal Oscillator • Programmable Reference Frequency Dividers • Phase Detector with Absolute Frequency Steering • Digital Lock Indicator • Double Edge Option on the Frequency Feedback Sensing Amplifier • Two High Current Op-Amps • 5V Reference Output Phase Locked Frequency Controller UC1633 UC2633 UC3633 FEATURES The UC1633 family of integrated circuits was designed for use in phase locked frequency control loops. While optimized for precision speed control of DC motors, these devices are universal enough for most ap- plications that require phase locked control. A precise reference fre- quency can be generated using the device’s high frequency oscillator and programmable frequency dividers. The oscillator operates using a broad range of crystals, or, can function as a buffer stage to an external frequency source. The phase detector on these integrated circuits compares the refer- ence frequency with a frequency/phase feedback signal. In the case of a motor, feedback is obtained at a hall output of other speed detection device. This signal is buffered by a sense ampilfier that squares up the signal as it goes into the digital phase detector. The phase detector re- sponds proportionally to the phase error between the reference and the sense amplifier output. This phase detector includes absolute fre- quency steering to provide maximum drive signals when any frequency error exists. This feature allows optimum start-up and lock times to be realized. Two op-amps are included that can be configured to provide necessary loop filtering. The outputs of the op-amps will source or sink in excess of 16mA, so they can provide a low impedence control signal to driving circuits. Additional features include a double edge option on the sense amplifier that can be used to double the loop reference frequency for increased loop bandwidths. A digital lock signal is provided that indicates when there is zero frequency error, and a 5V reference output allows DC op- erating levels to be accurately set. DESCRIPTION BLOCK DIAGRAM 1 |
Codice articolo simile - UC1633 |
|
Descrizione simile - UC1633 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |