Motore di ricerca datesheet componenti elettronici |
|
UC1633 Scheda tecnica(PDF) 5 Page - Texas Instruments |
|
UC1633 Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 8 page Phase Detector Operation The phase detector on these devices is a digital circuit that responds to the rising edges of the detector’s two in- puts. The phase detector output has three states: a high, 5V state, a low, 0V state, and a middle, 2.5V state. In the high and low states the output impedance of the detector is low and the middle state output impedence is high, typi- cally 6.0k Ω. When there is any static frequency difference between the inputs, the detector output is fixed at its high level if the +input (the sense amplifier signal) is greater in frequency, and fixed at its low level if the -input (the refer- ence frequency signal) is greater in frequency. When the frequencies of the two inputs to the detector are equal, the phase detector switches between its middle state and either the high or low states, depending on the relative phase of the two signals. If the +input is leading in phase then, during each period of the input frequency, the detector output will be high for a time equal to the time dif- ference between the rising edges of the inputs, and will be at its middle level for the remainder of the period. If the phase relationship is reversed, then the detector will go low for a time proportional to the phase difference of the inputs. The resulting gain of the phase detector. kø, is 5V/4 π radians or about 0.4V/radian. The dynamic range of the detector is ±2π radians. The operation of the phase detector is illustrated in the figures below. The upper figure shows typical voltage waveforms seen at the detector output for leading and lagging phase conditions. The lower figure is a state dia- gram of the phase detector logic. In this figure, the circles represent the 10 possible states of the logic, and the con- necting arrows represent the transition events/paths to and from these states. Transition arrows that have a clock- wise rotation are the result of a rising edge on the +input, and conversely, those with counter-clockwise rotation are tied to the rising edge of the -input signal. The normal operational states of the logic are 6 and 7 for positive phase error, 1 and 2 for a negative phase error. States 8 and 9 occur during positive frequency error, 3 and 4 during negative frequency error. States 5 and 10 occur only as the inputs cross over from the frequency er- ror to a normal phase error only condition. The level of the phase detector output is determined by the logic state as defined in the state diagram figure. The lock indicator out- put is high, off, when the detector is in states 1, 2, 6, or 7. UC1633 UC2633 UC3633 Typical Phase Detector Output Waveforms Phase Detector State Diagram APPLICATION AND OPERATION INFORMATION 5 |
Codice articolo simile - UC1633 |
|
Descrizione simile - UC1633 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |