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UC1573 Scheda tecnica(PDF) 2 Page - Texas Instruments |
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UC1573 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 5 page 2 UC1573 UC2573 UC3573 DIL-8, SOIC-8 (TOP VIEW) J or N, D Packages ABSOLUTE MAXIMUM RATINGS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V EAINV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6V to VCC IEAOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 4V CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VCC IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7A to 0.7A I3VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15mA Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C Currents are positive into, negative out of the specified termi- nal. Consult Packaging Section of Databook for thermal limita- tions and considerations of packages. CONNECTION DIAGRAMS ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these parameters apply for TA = –55°C to +125°C for the UC1573, –40°C to +85°C for the UC2573, and 0°C to +70°C for the UC3573, VCC = 5V, CT = 680pF, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Reference Section 3VREF 2.94 3 3.06 V Line Regulation VCC = 4.75 to 30V 1 10 mV Load Regulation I3VREF = 0 to –5mA 1 10 mV Oscillator Section Frequency VCC = 5V, 30V 85 100 115 kHz Error Amp Section EAINV EAOUT = 2V 1.45 1.5 1.55 V IEAINV EAOUT = 2V –0.2 –1 µA AVOL EAOUT = 0.5V to 3V 65 90 dB EAOUT High EAINV = 1.4V 3.6 4 4.4 V EAOUT Low EAINV = 1.6V 0.1 0.2 V IEAOUT EAINV = 1.4V, EAOUT = 2V –350 –500 µA EAINV = 1.6V, EAOUT = 2V 7 20 mA Unity Gain Bandwidth TJ = 25°C, F = 10kHz 0.6 1 MHz Current Sense Comparator Section Threshold (referred to VCC) –0.39 –0.43 –0.47 V Input Bias Current CS = VCC 150 800 nA CS Propagation Delay 400 ns Gate Drive Output Section OUT High Saturation IOUT = 0 0 0.3 V IOUT = –10mA 0.7 1.5 V IOUT = –100mA 1.5 2.5 V OUT Low Saturation IOUT = 10mA 0.1 0.4 V IOUT = 100mA 1.5 2.2 V Rise Time TJ = 25°C, CLOAD = 1nF + 3.3 Ohms 30 80 ns Fall Time TJ = 25°C, CLOAD = 1nF + 3.3 Ohms 30 80 ns Pulse Width Modulator Section Maximum Duty Cycle EAINV = 1.4V 92 96 % Minimum Duty Cycle EAINV = 1.6V 0 % Modulator Gain EAOUT = 1.5V to 2.5V 25 35 45 %/V Undervoltage Lockout Section Start Threshold 3.5 4.2 4.5 V Hysteresis 100 200 300 mV |
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