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TPA2051D3YFFR Scheda tecnica(PDF) 2 Page - Texas Instruments |
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TPA2051D3YFFR Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 33 page FUNCTIONAL BLOCK DIAGRAM + – BiasControl andPop Suppression MONO- Mux + Mode Control + SpeakerGuard ™ AGC PVDD 1 F m INL1 HPL HPR -60 dBto +18 dB VolumeControl SDA -60 dBto +18 dB VolumeControl SCL MONO+ Charge Pump 2.2 F m CPP CPN HPVSS PGND HPVDD HPVSS HPVDD HPVSS Voice- Mode Bypass Voice - Mode Bypass INR1 EN Gain Select: 0 dB to -12 dB 1.5 dB/ step PVDD PGND PWM H- Bridge VREF I2CInterface INL2 -60 dBto +18 dB VolumeControl INR2 DVDD Gain Select: +12 dB +6 dB OUT- OUT+ BYPASS+ BYPASS- HPVDD AGND AVDD 1 F m 1 F m 2.2 F m TPA2051D3 SLOS641 – JUNE 2009 ...................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPA2051D3 |
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