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TPA2017D2RTJR Scheda tecnica(PDF) 2 Page - Texas Instruments |
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TPA2017D2RTJR Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 20 page Interface & Control INL+ INL- AGC1 VoutL + VoutL - EN INR+ INR - AGC2 Class-D Modulator Volume Control Differential InputLeft CIN 1 F m Differential InputRight 1 F m Control Interface ICenable Power Stage AGC Reference Volume Control Power Stage VoutR + VoutR - AGND PGND Biasand References AVDD PVDDR PVDDL AGC Class-D Modulator CIN INL- INR+ INL+ INR- AGND AVDD PVDDL PVDDR 1 5 6 10 11 15 16 20 PVDDR PVDDL TPA2017D2 SLOS584 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM DEVICE PINOUT RTJ (QFN) PACKAGE (TOP VIEW) 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPA2017D2 |
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