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SN74SSTL16837 Scheda tecnica(PDF) 5 Page - Texas Instruments |
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SN74SSTL16837 Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 6 page SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION th tsu LOAD CIRCUIT Data Input Timing Input 1.9 V 1.1 V 1.9 V 1.1 V 1.9 V 1.1 V tw Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS PULSE DURATION Output Waveform 1 (see Note B) Output Waveform 2 (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ VTT 1.1 V VTT 1.9 V Output Control tPLH tPHL 1.9 V 1.1 V VOH VOL Input Output 25 Ω = SSTL_3 Class II 50 Ω = SSTL_3 Class I CL = 10 pF or 30 pF (see Note A) Test Point VTT 25 Ω VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns. D. The outputs are measured one at a time with one transition per measurement. E. VTT = VREF = VCC × 0.45 F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPHL and tPLH are the same as tpd. 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.1 V 1.1 V 1.9 V 1.9 V Figure 1. Load Circuit and Voltage Waveforms |
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