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SN74ACT7803-15DLR Scheda tecnica(PDF) 8 Page - Texas Instruments

Il numero della parte SN74ACT7803-15DLR
Spiegazioni elettronici  512 짰18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
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SN74ACT7803-15DLR Scheda tecnica(HTML) 8 Page - Texas Instruments

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SN74ACT7803
512
× 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS191C – MARCH 1991 – REVISED APRIL 1998
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
offset values for AF/AE
The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset
value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the
offsets are not programmed, the default values of X = Y = 64 are used. The AF/AE flag is high when the FIFO
contains X or fewer words or (512 – Y) or more words.
Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR
is high and WRTCLK is low. On the following low-to-high transition of WRTCLK, the binary value on D0–D7 is
stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another
low-to-high transition of WRTCLK reprograms Y to the binary value on D0–D7 at the time of the second
WRTCLK low-to-high transition. When the offsets are being programmed, writes to the FIFO memory are
disabled, regardless of the state of the write enables (WRTEN1, WRTEN2). A maximum value of 255 can be
programmed for either X or Y (see Figure 4). To use the default values of X = Y = 64, PEN must be held high.
34
RESET
WRTCLK
PEN
WRTEN1
WRTEN2
D0–D7
IR
X and Y
Y
Figure 4. Programming X and Y Separately
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to a disabled 3-state output
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θJA (see Note 1)
74
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
–65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.


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