SN74ABT3613

64

× 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F – JULY 1992 – REVISED APRIL 1998

8

POST OFFICE BOX 655303

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability

by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously

to one another. FF and AF are synchronized to CLKA. EF and AE are synchronized to CLKB. Table 4 shows

the relationship of each port flag to the level of FIFO fill.

Table 4. FIFO Flag Operation

NUMBER OF 36-BIT

WORDS IN THE FIFO†

SYNCHRONIZED

TO CLKB

SYNCHRONIZED

TO CLKA

WORDS IN THE FIFO†

EF

AE

AF

FF

0

L

L

H

H

1 to X

H

L

H

H

(X + 1) to [64 – (X + 1)]

H

H

H

H

(64 – X) to 63

H

H

L

H

64

H

H

L

L

† X is the value in the AE flag and AF flag offset register.

empty flag (EF)

The FIFO EF is synchronized to the port clock that reads data from its array (CLKB). When the empty flag is

high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and

attempted FIFO reads are ignored. When reading the FIFO with a byte or word size on port B, EF is set low when

the fourth byte or second word of the last long word is read.

The FIFO read pointer is incremented each time a new word is clocked to the output register. A word written

to the FIFO can be read to the FIFO output register in a minimum of three port-B clock (CLKB) cycles. An EF

is low if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock

that reads data from the FIFO have not elapsed since the time the word was written. The FIFO EF is set high

by the second low-to-high transition of CLKB and the new data word can be read to the FIFO output register

in the following cycle.

A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs

cycle (see Figure 9).

full flag (FF)

The FIFO FF is synchronized to the port clock that writes data to its array (CLKA). When FF is high, a memory

location is free in the SRAM to receive new data. No memory locations are free when FF is low and attempted

writes to the FIFO are ignored.

Each time a word is written to the FIFO, the write pointer is incremented. From the time a word is read from the

FIFO, the previous memory location is ready to be written in a minimum of three CLKA cycles. FF is low if fewer

than two CLKA cycles have elapsed since the next memory-write location has been read. The second

low-to-high transition on the FF synchronizing clock after the read sets the FF high and data can be written in

the following clock cycle.

A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs

cycle (see Figure 10).